PIC16F785-E/SS Microchip Technology, PIC16F785-E/SS Datasheet - Page 120

• Manufacturer Part Number: PIC16F785-E/SS
• Description: 20 PIN, 3.5 KB STD FLASH, 128 RAM, 18 I/O PB FREE,
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F785-E/SS

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT20SS1-1 - SOCKET TRANSITION 20DIP 20SSOPAC162060 - HEADER INTRFC MPLAB ICD2 20PIN
• Connectivity: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F785/HV785
15.3.1
External interrupt on RA2/AN2/T0CKI/INT/C1OUT pin
is edge-triggered; either rising, if INTEDG bit of the
OPTION Register is set, or falling, if INTEDG bit is
clear. When a valid edge appears on the RA2/AN2/
T0CKI/INT/C1OUT pin, the INTF bit of the INTCON
Register is set. This interrupt can be disabled by clear-
ing the INTE control bit of the INTCON Register. The
INTF bit must be cleared in software in the Interrupt
Service Routine before re-enabling this interrupt. The
RA2/AN2/T0CKI/INT/C1OUT interrupt can wake-up
the processor from Sleep if the INTE bit was set prior to
going into Sleep. The status of the GIE bit decides
whether or not the processor branches to the interrupt
vector following wake-up (0004h). See Section 15.6
“Power-Down Mode (Sleep)” for details on Sleep and
Figure 15-10 for timing of wake-up from Sleep through
RA2/AN2/T0CKI/INT/C1OUT interrupt.
FIGURE 15-7:
DS41249E-page 118
Note:
RA2/AN2/T0CKI/INT/C1OUT
INTERRUPT
The ANSEL0 (91h), and ANSEL1 (93h)
registers must be initialized to configure
an analog channel as a digital input. Pins
configured as analog inputs will read ‘0’.
IOC-RA0
IOC-RA1
IOC-RA2
IOC-RA3
IOC-RA4
IOC-RA5
TMR2IF
TMR2IE
TMR1IE
TMR1IF
CCP1IF
CCP1IE
IOCA0
IOCA1
IOCA2
IOCA3
IOCA4
IOCA5
OSFIF
OSFIE
ADIF
ADIE
EEIE
C1IF
C1IE
C2IF
C2IE
EEIF
INTERRUPT LOGIC
Note 1:
RAIE
INTF
INTE
RAIF
PEIE
T0IF
T0IE
GIE
Some peripherals depend upon the system clock for
operation. Since the system clock is suspended during Sleep, only
those peripherals which do not depend upon the system clock will wake
the part from Sleep. See Section 15.6.1 “Wake-up from Sleep”.
15.3.2
An overflow (FFh → 00h) in the TMR0 register will set
the T0IF bit of the INTCON Register. The interrupt can
be enabled/disabled by setting/clearing T0IE bit of the
INTCON Register. See Section 5.0 “Timer0 Module”
for operation of the Timer0 module.
15.3.3
An input change on PORTA change sets the RAIF of
the INTCON Register bit. The interrupt can be enabled/
disabled by setting/clearing the RAIE bit of the INTCON
Register. Plus, individual pins can be configured
through the IOCA register.
Note:
TMR0 INTERRUPT
PORTA INTERRUPT
If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RAIF inter-
rupt flag may not get set.
Wake-up (If in Sleep mode)
© 2008 Microchip Technology Inc.
Interrupt to CPU
(1)