PIC16F886-E/SS Microchip Technology, PIC16F886-E/SS Datasheet - Page 176
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PIC16F886-E/SS
Manufacturer Part Number
PIC16F886-E/SS
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SSOP,28PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.MCP1631RD-MCC2.pdf
(328 pages)
3.PIC16F882-ISS.pdf
(16 pages)
4.PIC16F882-ISS.pdf
(36 pages)
Specifications of PIC16F886-E/SS
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
14KB (8K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-SSOP
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
368 B
Interface Type
MSSP, EUSART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
24
Number Of Timers
3
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM164123, DM164120-3, DV164122
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 11 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM164123 - KIT MANAGEMENT SYSTEM PICDEM
Lead Free Status / Rohs Status
Details
- PIC16F616T-ISL PDF datasheet
- MCP1631RD-MCC2 PDF datasheet #2
- PIC16F882-ISS PDF datasheet #3
- PIC16F882-ISS PDF datasheet #4
- Current page: 176 of 328
- Download datasheet (6Mb)
PIC16F882/883/884/886/887
FIGURE 12-12:
TABLE 12-8:
DS41291F-page 174
BAUDCTL ABDOVF
INTCON
PIE1
PIR1
RCREG
RCSTA
SPBRG
SPBRGH
TRISC
TXREG
TXSTA
Legend:
(SCKP = 0)
(SCKP = 1)
(Interrupt)
Note:
Name
TX/CK pin
TX/CK pin
SREN bit
CREN bit
bit SREN
RCIF bit
RXREG
RX/DT
Write to
Read
pin
x = unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Master Reception.
EUSART Receive Data Register
EUSART Transmit Data Register
Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
‘0’
TRISC7
BRG15
SPEN
BRG7
CSRC
Bit 7
GIE
—
—
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
TRISC6
BRG14
RCIDL
BRG6
PEIE
ADIE
ADIF
Bit 6
RX9
TX9
bit 0
TRISC5
BRG13
SREN
BRG5
TXEN
RCIE
RCIF
Bit 5
T0IE
—
bit 1
TRISC4
BRG12
CREN
BRG4
SYNC
SCKP
INTE
Bit 4
TXIE
TXIF
bit 2
ADDEN
TRISC3
SENDB
BRG16
BRG11
SSPIE
SSPIF
BRG3
RBIE
Bit 3
bit 3
CCP1IE
CCP1IF
TRISC2
BRG10
FERR
BRG2
BRGH
Bit 2
T0IF
—
bit 4
TMR2IE
TMR2IF
TRISC1
OERR
TRMT
BRG1
BRG9
WUE
Bit 1
INTF
bit 5
TMR1IE
TMR1IF
TRISC0
ABDEN
RX9D
BRG0
BRG8
TX9D
Bit 0
RBIF
© 2009 Microchip Technology Inc.
bit 6
01-0 0-00
0000 000x
-000 0000
-000 0000
0000 0000
0000 000x
0000 0000
0000 0000
1111 1111
0000 0000
0000 0010
POR, BOR
Value on
bit 7
01-0 0-00
0000 000x
-000 0000
-000 0000
0000 0000
0000 000x
0000 0000
0000 0000
1111 1111
0000 0000
0000 0010
Value on
all other
Resets
‘0’
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