PIC16F886-E/SS Microchip Technology, PIC16F886-E/SS Datasheet - Page 224
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PIC16F886-E/SS
Manufacturer Part Number
PIC16F886-E/SS
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SSOP,28PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.MCP1631RD-MCC2.pdf
(328 pages)
3.PIC16F882-ISS.pdf
(16 pages)
4.PIC16F882-ISS.pdf
(36 pages)
Specifications of PIC16F886-E/SS
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
14KB (8K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-SSOP
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
368 B
Interface Type
MSSP, EUSART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
24
Number Of Timers
3
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM164123, DM164120-3, DV164122
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 11 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM164123 - KIT MANAGEMENT SYSTEM PICDEM
Lead Free Status / Rohs Status
Details
- PIC16F616T-ISL PDF datasheet
- MCP1631RD-MCC2 PDF datasheet #2
- PIC16F882-ISS PDF datasheet #3
- PIC16F882-ISS PDF datasheet #4
- Current page: 224 of 328
- Download datasheet (6Mb)
PIC16F882/883/884/886/887
FIGURE 14-8:
TABLE 14-6:
DS41291F-page 222
INTCON
PIE1
PIE2
PIR1
PIR2
Legend:
INSTRUCTION FLOW
(INTCON<7>)
(INTCON<1>)
CLKOUT
Name
Note 1: INTF flag is sampled here (every Q1).
Instruction
Executed
Instruction
Fetched
INTF flag
INT pin
GIE bit
OSC1
2: Asynchronous interrupt latency = 3-4 T
3: CLKOUT is available only in INTOSC and RC Oscillator modes.
4: For minimum width of INT pulse, refer to AC specifications in Section 17.0 “Electrical Specifications”.
5: INTF is enabled to be set any time during the Q4-Q1 cycles.
PC
x = unknown, u = unchanged, — = unimplemented read as ‘0’, q = value depends upon condition.
Shaded cells are not used by the Interrupt module.
(3)
is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
OSFIE
OSFIF
Bit 7
GIE
—
—
SUMMARY OF INTERRUPT REGISTERS
Q1
Inst (PC – 1)
Inst (PC)
(1)
INT PIN INTERRUPT TIMING
Q2
PC
PEIE
ADIE
C2IE
ADIF
Bit 6
C2IF
(4)
Q3
Q4
(5)
RCIE
RCIF
Bit 5
C1IE
C1IF
T0IE
Q1
Inst (PC + 1)
Inst (PC)
Q2
(1)
INTE
EEIE
Bit 4
TXIE
TXIF
EEIF
PC + 1
Q3
CY
. Synchronous latency = 3 T
Q4
SSPIE
BCLIE
SSPIF
BCLIF
RBIE
Bit 3
Interrupt Latency
Q1
Dummy Cycle
ULPWUIE
ULPWUIF
Q2
CCP1IE
CCP1IF
PC + 1
Bit 2
T0IF
—
Q3
Q4
(2)
TMR2IE
TMR2IF
Bit 1
INTF
CY
—
—
, where T
Q1
Dummy Cycle
Inst (0004h)
Q2
TMR1IE
CCP2IE
TMR1IF
CCP2IF
0004h
Bit 0
RBIF
CY
= instruction cycle time. Latency
Q3
© 2009 Microchip Technology Inc.
Q4
0000 000x
-000 0000
0000 00-0
-000 0000
0000 00-0
POR, BOR
Value on
Q1
Inst (0005h)
Q2
Inst (0004h)
0005h
0000 000x
-000 0000
0000 00-0
-000 0000
0000 00-0
Q3
Value on
all other
Resets
Q4
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