PIC18C601-I/L Microchip Technology, PIC18C601-I/L Datasheet
PIC18C601-I/L
Specifications of PIC18C601-I/L
Available stocks
Related parts for PIC18C601-I/L
PIC18C601-I/L Summary of contents
Page 1
... I C™ Master and Slave mode • Addressable USART module: Supports Interrupt on Address bit 2001 Microchip Technology Inc. PIC18C601/801 Advanced Analog Features: • 10-bit Analog-to-Digital Converter module (A/D) with: - Fast sampling rate - Conversion available during SLEEP - DNL = ±1 LSb, INL = ±1 LSb ...
Page 2
... PIC18C601/801 Pin Diagrams 64-Pin TQFP RE1/AD9 2 RE0/AD8 3 RG0/ALE 4 RG1/OE 5 RG2/WRL 6 RG3/WRH 7 MCLR RG4/BA0 RF7/UB 12 RF6/LB 13 RF5/CS1 14 RF4/A16 15 RF3/CSIO 16 RF2/AN7 DS39541A-page 2 PIC18C601 Advance Information 48 RB0/INT0 47 RB1/INT1 46 RB2/INT2 45 RB3/CCP2 44 RB4 43 RB5 42 RB6 OSC2/CLKO 39 OSC1/CLKI RB7 36 RC5/SDO 35 RC4/SDI/SDA 34 RC3/SCK/SCL 33 RC2/CCP1 2001 Microchip Technology Inc. ...
Page 3
... Pin Diagrams (Cont.’d) 68-Pin PLCC RE1/AD9 11 RE0/AD8 12 RG0/ALE 13 RG1/OE 14 RG2/WRL 15 RG3/WRH 16 MCLR RG4/BA0 RF7/UB RF6/LB 22 RF5/CS1 23 RF4/A16 24 RF3/CSIO 25 26 RF2/AN7 2001 Microchip Technology Inc. PIC18C601/801 PIC18C601 Advance Information 60 RB0/INT0 59 RB1/INT1 58 RB2/INT2 57 RB3/CCP2 56 RB4 55 RB5 54 RB6 OSC2/CLKO 50 OSC1/CLKI RB7 47 RC5/SDO 46 RC4/SDI/SDA 45 RC3/SCK/SCL 44 RC2/CCP1 DS39541A-page 3 ...
Page 4
... PIC18C601/801 Pin Diagrams (Cont.’d) 80-Pin TQFP RH2/A18 2 RH3/A19 3 RE1/AD9 RE0/AD8 4 RG0/ALE 5 RG1/OE 6 RG2/WRL 7 8 RG3/WRH 9 MCLR/V PP RG4/BA0 RF7/UB 14 RF6/LB RF5/CS1 15 16 RF4/CS2 RF3/CSIO 17 RF2/AN7 18 19 RH4/AN8 20 RH5/AN9 DS39541A-page PIC18C801 Advance Information 60 RJ5/D5 59 RJ4/D4 58 RB0/INT0 57 RB1/INT1 56 RB2/INT2 55 RB3/CCP2 RB4 54 53 RB5 ...
Page 5
... PLCC RH2/A18 12 13 RH3/A19 RE1/AD9 14 RE0/AD8 15 RG0/ALE 16 RG1/OE 17 RG2/WRL 18 RG3/WRH 19 MCLR RG4/BA0 RF7/UB 25 RF6/LB 26 RF5/CS1 27 RF4/CS2 28 RF3/CSIO 29 RF2/AN7 30 RH4/AN8 31 RH5/AN9 2001 Microchip Technology Inc. PIC18C601/801 PIC18C801 Advance Information 75 RJ5/ RJ4/D4 RB0/INT0 72 RB1/INT1 71 RB2/INT2 70 69 RB3/CCP2 68 RB4 67 RB5 66 RB6 OSC2/CLKO 62 OSC1/CLKI RB7 59 ...
Page 6
... PIC18C601/801 Table of Contents 1.0 Device Overview.................................................................................................................................................. 9 2.0 Oscillator Configurations.................................................................................................................................... 21 3.0 RESET............................................................................................................................................................... 29 4.0 Memory Organization ........................................................................................................................................ 39 5.0 External Memory Interface................................................................................................................................. 63 6.0 Table Reads/Table Writes ................................................................................................................................. 73 7 Hardware Multiplier .................................................................................................................................. 85 8.0 Interrupts............................................................................................................................................................ 89 9.0 I/O Ports........................................................................................................................................................... 103 10.0 Timer0 Module................................................................................................................................................. 127 11.0 Timer1 Module................................................................................................................................................. 130 12.0 Timer2 Module................................................................................................................................................. 135 13 ...
Page 7
... When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include liter- ature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products. 2001 Microchip Technology Inc. PIC18C601/801 Advance Information DS39541A-page 7 ...
Page 8
... PIC18C601/801 NOTES: DS39541A-page 8 Advance Information 2001 Microchip Technology Inc. ...
Page 9
... DEVICE OVERVIEW This document contains device specific information for the following two devices: 1. PIC18C601 2. PIC18C801 The PIC18C601 is available in 64-pin TQFP and 68-pin PLCC packages. The PIC18C801 is available in 80-pin TQFP and 84-pin PLCC packages. TABLE 1-1: DEVICE FEATURES Features Operating Frequency Bytes External Max ...
Page 10
... PIC18C601/801 FIGURE 1-1: PIC18C601 BLOCK DIAGRAM AD7:AD0 Table Pointer<21> 21 inc/dec logic 21 20 PCLATU 21 Address Latch Program Memory (up to 256 Kbytes) Data Latch 16 Table Latch 8 ROM Latch A16, AD15:AD8 Instruction Decode & Control OSC2/CLKO OSC1/CLKI Timing T1OSI Generation T1OSO Timer0 Timer1 CCP1 ...
Page 11
... Start-upTimer 8 8 Power-on Reset 8 Watchdog Timer ALU<8> Low Voltage Detect 8 MCLR Timer2 Timer3 Synchronous USART1 Serial Port Advance Information PIC18C601/801 PORTA RA0/AN0 RA1/AN1 RA2/AN2/V - REF RA3/AN3/V + REF RA4/T0CKI RA5/AN4/SS/LVDIN PORTB RB0/INT0 RB1/INT1 RB2/INT2 RB3/CCP2 RB4 RB5 RB6 RB7 PORTC RC0/T1OSO/T13CKI RC1/T1OSI ...
Page 12
... PIC18C601/801 TABLE 1-2: PINOUT I/O DESCRIPTIONS Pin Number Pin Name PIC18C601 TQFP PLCC MCLR MCLR — 1, 18, 35, 52 OSC1/CLKI 39 50 OSC1 CLKI OSC2/CLKO 40 51 OSC2 CLKO Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I = Input P = Power DS39541A-page 12 Pin ...
Page 13
... ST I Analog CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open Drain (no P diode to V Advance Information PIC18C601/801 Digital I/O. Analog input 0. Digital I/O. Analog input 1. Digital I/O. Analog input 2. A/D reference voltage (Low) input. Digital I/O. Analog input 3. A/D reference voltage (High) input. ...
Page 14
... PIC18C601/801 TABLE 1-2: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18C601 TQFP PLCC RB0/INT0 48 60 RB0 INT0 RB1/INT1 47 59 RB1 INT1 RB2/INT2 46 58 RB2 INT2 RB3/CCP2 45 57 RB3 CCP2 RB4 44 56 RB5 43 55 RB6 42 54 RB7 37 48 Legend: TTL = TTL compatible input ...
Page 15
... ST I/O ST CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open Drain (no P diode to V Advance Information PIC18C601/801 Digital I/O. Timer1 oscillator output. Timer1/Timer3 external clock input. Digital I/O. Timer1 oscillator input. Digital I/O. Capture1 input/Compare1 output/PWM1 output. Digital I/O. Synchronous serial clock input/output for SPI mode ...
Page 16
... PIC18C601/801 TABLE 1-2: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18C601 TQFP PLCC RD0/AD0 58 3 RD0 AD0 RD1/AD1 55 67 RD1 AD1 RD2/AD2 54 66 RD2 AD2 RD3/AD3 53 65 RD3 AD3 RD4/AD4 52 64 RD4 AD4 RD5/AD5 51 63 RD5 AD5 RD6/AD6 50 62 RD6 ...
Page 17
... ST I/O ST CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open Drain (no P diode to V Advance Information PIC18C601/801 Digital I/O. External memory address/data 8. Digital I/O. External memory address/data 9. Digital I/O. External memory address/data 10. Digital I/O. External memory address/data 11. Digital I/O. External memory address/data 12. ...
Page 18
... PIC18C601/801 TABLE 1-2: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18C601 TQFP PLCC RF0/AN5 18 28 RF0 AN5 RF1/AN6 17 27 RF1 AN6 RF2/AN7 16 26 RF2 AN7 RF3/CSIO 15 25 RF3 CSIO RF4/A16 14 24 RF4/CS2 — — RF4 A16 CS2 RF5/CS1 13 23 RF5 ...
Page 19
... ST I Analog CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open Drain (no P diode to V Advance Information PIC18C601/801 Digital I/O. Address Latch Enable. Digital I/O. Output Enable. Digital I/O. Write Low control. Digital I/O. Write High control. Digital I/O. System bus byte address 0. ...
Page 20
... PIC18C601/801 TABLE 1-2: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18C601 TQFP PLCC — — RJ0/D0 RJ0 D0 — — RJ1/D1 RJ1 D1 RJ2/D2 — — RJ2 D2 — — RJ3/D3 RJ3 D3 — — RJ4/D4 RJ4 D4 RJ5/D5 — — RJ5 D5 — — RJ6/D6 ...
Page 21
... OSCILLATOR CONFIGURATIONS 2.1 Oscillator Types PIC18C601/801 can be operated in one of four oscilla- tor modes, programmable by configuration bits FOSC1:FOSC0 in CONFIG1H register Low Power Crystal 2. HS High Speed Crystal/Resonator 3. RC External Resistor/Capacitor 4. EC External Clock 2.2 Crystal Oscillator/Ceramic Resonators oscillator modes, a crystal or ceramic res- onator is connected to the OSC1 and OSC2 pins to establish oscillation ...
Page 22
... PPM ± 20 PPM C EXT ± 50 PPM V SS ± 50 PPM F ± 30 PPM or I/O ± 30 PPM Recommended values: Advance Information ) values and the operat- EXT RC OSCILLATOR MODE Internal OSC1 Clock PIC18C601/801 OSC2/CLKO /4 OSC 100 k EXT C > 20pF EXT 2001 Microchip Technology Inc. ...
Page 23
... PLLEN bit in OSCCON register is clear, the PLL is not enabled and the system clock will come directly from OSC1. HS oscillator mode is the default for PIC18C601/801. In all other modes, the PLLEN bit and the SCS1 bit are forced to ‘0’. ...
Page 24
... PIC18C601/801 2.6 Oscillator Switching Feature PIC18C601/801 devices include a feature that allows the system clock source to be switched from the main oscillator to an alternate low frequency clock source. For PIC18C601/801 devices, this alternate clock source is the Timer1 oscillator low frequency crys- tal (32 kHz, for example) has been attached to the ...
Page 25
... R = Readable bit - n = Value at POR 2.6.2 OSCILLATOR TRANSITIONS PIC18C601/801 devices contain circuitry to prevent "glitches" when switching between oscillator sources. Essentially, the circuitry waits for eight rising edges of the clock source that the processor is switching to. This ensures that the new clock source is stable and that its pulse width will not be less than the shortest pulse width of the two clock sources ...
Page 26
... PIC18C601/801 FIGURE 2-6: TIMING DIAGRAM FOR TRANSITION FROM OSC1 TO TIMER1 OSCILLATOR T1OSI OSC1 T OSC Internal System T DLY Clock SCS0 (OSCCON<0>) Program PC Counter Note: Delay on internal system clock is eight oscillator cycles for synchronization. FIGURE 2-7: TIMING DIAGRAM FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS, LP) ...
Page 27
... A timing diagram indicating the transition from the Timer1 oscillator to the main oscilla- tor for RC and EC modes is shown in Figure 2-10 PLL T SCS T OSC OSC T SCS T PLL Advance Information PIC18C601/801 is not PLL DS39541A-page 27 ...
Page 28
... T #33) on power-up only. The second timer is the Oscil- lator Start-up Timer (OST), intended to keep the chip in RESET until the crystal oscillator is stable. PIC18C601/801 devices provide a configuration bit, PWRTEN in CONFIG2L register, to enable or disable the Power-up Timer. By default, the Power-up Timer is enabled. ...
Page 29
... RESET. See Table 3-3 for a full description of the RESET states of all registers. A simplified block diagram of the on-chip RESET circuit is shown in Figure 3-1. PIC18C601/801 has a MCLR noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. A WDT Reset does not drive MCLR pin low. ...
Page 30
... Bringing MCLR high will begin execution immediately (Figure 3-5). This is useful for testing purposes or to synchronize more than one PIC18C601/801 device operating in parallel. Table 3-2 shows the RESET conditions for some Special Function Registers, while Table 3-3 shows the RESET conditions for all registers ...
Page 31
... ur-u 00ur u ( ur-u 00ur u Advance Information PIC18C601/801 Wake-up from SLEEP or (1) Oscillator Switch 1024T + 1 ms OSC 1024T OSC — — R/W-1 R/W-1 U POR r bit POR STKFUL STKUNF ...
Page 32
... PIC18C601/801 FIGURE 3-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 3-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 3-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO V ...
Page 33
... FIGURE 3-7: TIME-OUT SEQUENCE ON POR W/ PLL ENABLED (MCLR TIED MCLR IINTERNAL POR PWRT TIME-OUT OST TIME-OUT PLL TIME-OUT INTERNAL RESET T = 1024 clock cycles. OST max. First three stages of the PWRT timer. PLL 2001 Microchip Technology Inc. PIC18C601/801 ) DEADTIME T PWRT T OST T PWRT T OST T ...
Page 34
... PIC18C601/801 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS Applicable Register Power-on Reset Devices TOSU 601 801 TOSH 601 801 TOSL 601 801 STKPTR 601 801 PCLATU 601 801 PCLATH 601 801 PCL 601 801 TBLPTRU 601 801 TBLPTRH 601 801 TBLPTRL ...
Page 35
... Advance Information PIC18C601/801 Wake-up via WDT or Interrupt (Note 5) (Note 5) (Note 5) (Note 5) ---- uuuu uuuu uuuu ---u uuuu uuuu uuuu uuuu uuuu uuuu uuuu --uu u-uu ...
Page 36
... PIC18C601/801 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Register Power-on Reset Devices CCPR2H 601 801 CCPR2L 601 801 CCP2CON 601 801 TMR3H 601 801 TMR3L 601 801 T3CON 601 801 SPBRG 601 801 RCREG 601 801 TXREG 601 801 ...
Page 37
... Advance Information PIC18C601/801 Wake-up via WDT or Interrupt uuuu uuuu uuuu uuuu uuuu uuuu --uu uuuu uuuu uuuu uuuu uuuu ---u uuuu uuuu uuuu uuuu uuuu ...
Page 38
... PIC18C601/801 NOTES: DS39541A-page 38 Advance Information 2001 Microchip Technology Inc. ...
Page 39
... PIC18C601/801 devices have a 31-level stack to store the program counter values during subroutine calls and interrupts. Figure 4-1 shows the program memory map and stack for PIC18C601. Figure 4-2 shows the program memory map and stack for the PIC18C801. 2001 Microchip Technology Inc. ...
Page 40
... PIC18C601/801 FIGURE 4-1: PROGRAM MEMORY MAP AND STACK FOR PIC18C601 (PGRM = 0) PC<20:0> 21 Stack Level 1 Stack Level 31 RESET Vector 0000h High Priority Interrupt Vector 0008h Low Priority Interrupt Vector 0018h External Program Memory 3FFFFh 40000h Read ’0’ 1FFFFFh DS39541A-page 40 FIGURE 4-2: PC< ...
Page 41
... FIGURE 4-3: PROGRAM MEMORY MAP AND STACK FOR PIC18C601 (PGRM = 1) On-Chip Boot RAM INTERNAL MEMORY 2001 Microchip Technology Inc. PIC18C601/801 PC<20:0> 21 Stack Level 1 Stack Level 31 RESET Vector High Priority Interrupt Vector Low Priority Interrupt Vector External Program Memory Read ’0’ ...
Page 42
... PIC18C601/801 FIGURE 4-4: PROGRAM MEMORY MAP AND STACK FOR PIC18C801 (PGRM = 1) On-Chip Boot RAM INTERNAL MEMORY DS39541A-page 42 PC<20:0> 21 Stack Level 1 Stack Level 31 RESET Vector High Priority Interrupt Vector Low Priority Interrupt Vector External Program Memory 1FFE00h External Table Memory 1FFFFFh EXTERNAL MEMORY ...
Page 43
... SFR registers. Status bits STKOVF and STKUNF in STKPTR register, indicate whether stack over/underflow has occurred or not. 2001 Microchip Technology Inc. PIC18C601/801 4.2.1 TOP-OF-STACK ACCESS The top of the stack is readable and writable. Three register locations, TOSU, TOSH and TOSL, allow access to the contents of the stack location indicated by the STKPTR register ...
Page 44
... PIC18C601/801 REGISTER 4-1: STKPTR - STACK POINTER REGISTER R/C-0 R/C-0 STKFUL STKUNF bit 7 bit 7 STKFUL: Stack Full Flag bit 1 = Stack became full or overflowed 0 = Stack has not become full or overflowed bit 6 STKUNF: Stack Underflow Flag bit 1 = Stack underflow occurred 0 = Stack underflow did not occur ...
Page 45
... STKFUL or STKUNF bit and then cause a RESET. The STKFUL or STKUNF bits are only cleared by the user software or a POR. 2001 Microchip Technology Inc. PIC18C601/801 4.3 Fast Register Stack A “fast return” option is available for interrupts and calls. A fast register stack is provided for the STATUS, WREG and BSR registers, and is only one layer in depth ...
Page 46
... PIC18C601/801 4.4 PCL, PCLATH and PCLATU The program counter (PC) specifies the address of the instruction to fetch for execution. The PC is 21-bits wide. The low byte is called the PCL register. This reg- ister is readable and writable. The high byte is called the PCH register. This register contains the PC<15:8> ...
Page 47
... MOVLW 055h GOTO 000006h MOVFF 123h, 456h — 2001 Microchip Technology Inc. PIC18C601/801 4.7 Instructions in Program Memory The program memory is addressed in bytes. Instruc- tions are stored as two bytes or four bytes in program memory. The Least Significant Byte of an instruction word is always stored in a program memory location with an even address (LSB = ’ ...
Page 48
... PIC18C601/801 4.7.1 TWO-WORD INSTRUCTIONS PIC18C601/801 devices have four two-word instruc- tions: MOVFF, CALL, GOTO and LFSR. The second word of these instructions has the four MSB’s set to 1’s and is a special kind of NOP instruction. The lower 12 bits of the second word contain data to be used by the instruction ...
Page 49
... Indirect addressing operates through the File Select Registers (FSR). The operation of indirect addressing is shown in Section 4.12. PIC18C601/801 devices have banked memory in the GPR area. GPRs are not initialized by a Power-on Reset and are unchanged on all other RESETS. Data RAM is available for use as GPR registers by all instructions. Bank 15 (0F80h to 0FFFh) contains SFR’ ...
Page 50
... PIC18C601/801 REGISTER 4-2: PSPCON REGISTER U-0 — bit 7 bit 7-2 Unimplemented: Read as '0' bit 1-0 CMLK<1:0>: Combination Lock bits Legend Readable bit - n = Value at POR The Combination Lock bits must be set sequentially, meaning that as soon as Combination Lock bit CMLK1 is set, the second Combination Lock bit CMLK0 must be set on the following instruction cycle ...
Page 51
... GPR 5FFh Unused Read ’00h’ EFFh F00h Unused F7Fh F80h Access SFR’s FFFh Advance Information PIC18C601/801 Access RAM Bank 00h Access Bank Low (GPR’s) 7Fh 80h Access Bank High (SFR’s) FFh When the BSR is ignored and this Access RAM bank is used ...
Page 52
... PIC18C601/801 FIGURE 4-8: DATA MEMORY MAP FOR PIC18C601/801 (PGRM = 1) BSR<3:0> 00h = 0000b Bank 0 FFh 00h = 0001b Bank 1 FFh 00h = 0010b Bank 2 FFh 00h = 0011b Bank 3 FFh = 0100b Bank 1110b Bank 14 00h = 1111b Bank 15 FFh DS39541A-page 52 Data Memory Map 000h Access GPR’s ...
Page 53
... POSTDEC1 FC5h FE4h PREINC1 FC4h FE3h PLUSW1 FC3h FE2h FSR1H FC2h FE1h FSR1L FC1h FE0h BSR FC0h 2001 Microchip Technology Inc. PIC18C601/801 INDF2 FBFh CCPR1H POSTINC2 FBEh CCPR1L POSTDEC2 FBDh CCP1CON F9Dh PREINC2 FBCh CCPR2H PLUSW2 FBBh CCPR2L FSR2H FBAh CCP2CON F9Ah ...
Page 54
... PIC18C601/801 TABLE 4-2: REGISTER FILE SUMMARY - PIC18C601/801 File Name Bit 7 Bit 6 FFFh TOSU — — FFEh TOSH Top-of-Stack High Byte (TOS<15:8>) FFDh TOSL Top-of-Stack Low Byte (TOS<7:0>) FFCh STKPTR STKOVF STKUNF FFBh PCLATU — — FFAh PCLATH Holding Register for PC<15:8> ...
Page 55
... TABLE 4-2: REGISTER FILE SUMMARY - PIC18C601/801 (CONTINUED) File Name Bit 7 Bit 6 FD7h TMR0H Timer0 Register High Byte FD6h TMR0L Timer0 Register Low Byte FD5h T0CON TMR0ON 16BIT FD4h Reserved (2) FD3h OSCCON — — (2) FD2h LVDCON — — (2) FD1h WDTCON — — ...
Page 56
... PIC18C601/801 TABLE 4-2: REGISTER FILE SUMMARY - PIC18C601/801 (CONTINUED) File Name Bit 7 Bit 6 FB0h PSPCON — — FAFh SPBRG USART Baud Rate Generator FAEh RCREG USART Receive Register FADh TXREG USART Transmit Register FACh TXSTA CSRC TX9 FABh RCSTA SPEN RX9 FAAh ...
Page 57
... TABLE 4-2: REGISTER FILE SUMMARY - PIC18C601/801 (CONTINUED) File Name Bit 7 Bit 6 F84h PORTE Read PORTE Pins, Write PORTE Data Latch F83h PORTD Read PORTD pins, Write PORTD Data Latch F82h PORTC Read PORTC pins, Write PORTC Data Latch F81h PORTB Read PORTB pins, Write PORTB Data Latch ...
Page 58
... PIC18C601/801 4.10 Access Bank The Access Bank is an architectural enhancement that is very useful for C compiler code optimization. The techniques used by the C compiler are also useful for programs written in assembly. This data memory region can be used for: • Intermediate computational values • Local variables of subroutines • ...
Page 59
... WREG register and the value in FSR to form the address before an indirect access. The FSR value is not changed indirect addressing operation is done where the target address is an FSRnH or FSRnL register, the write operation will dominate over the pre- or post- increment/decrement functions. Advance Information PIC18C601/801 DS39541A-page 59 ...
Page 60
... PIC18C601/801 FIGURE 4-11: INDIRECT ADDRESSING 11 FSRnH Location Select Note 1: For register file map detail, see Table 4-2. DS39541A-page 60 Indirect Addressing FSR Register FSRnL 0000h Data (1) Memory 0FFFh Advance Information 2001 Microchip Technology Inc. ...
Page 61
... The C and DC bits operate as a borrow and digit borrow bit respectively, in subtraction. U-0 U-0 R/W-x R/W-x — — Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared Advance Information PIC18C601/801 R/W-x R/W-x R/W bit Bit is unknown DS39541A-page 61 ...
Page 62
... PIC18C601/801 4.14 RCON Register The Reset Control (RCON) register contains flag bits that allow differentiation between the sources of a device RESET. These flags include the TO, PD, POR and RI bits. This register is readable and writable. REGISTER 4-4: RCON REGISTER R/W-0 IPEN bit 7 ...
Page 63
... FLASH, EPROM, SRAM, etc. Memory mapped peripherals may also be accessed. The External Memory Interface physical implementa- tion includes pins on the PIC18C601 and pins on the PIC18C801. These pins are reserved for external address/data bus functions. REGISTER 5-1: MEMCON REGISTER ...
Page 64
... The least significant bit of the address, BA0, must be connected to the memory devices in this mode. Figure 5-1 shows an example of 8-bit Multiplexed mode on the PIC18C601. The control signals used in 8-bit Multiplexed mode are outlined in Table 5-1. Register 5-2 describes 8-bit Multiplexed mode timing. ...
Page 65
... Therefore, the designer must choose external memory devices according to timing calculations, based on 1 times instruction rate). For proper memory speed CY selection, setup and hold times must be considered. 2001 Microchip Technology Inc. PIC18C601/801 Q3 Q2 03Ah ABh 55h Opcode Fetch MOVLW 55h ...
Page 66
... PIC18C601/801 FIGURE 5-3: 8-BIT DE-MULTIPLEXED MODE EXAMPLE BA0 A<19:16>, AD<15:0> D<7:0> PIC18C801 ALE CS1 OE WRL Note 1: This signal only applies to Table Writes. See Section 6.0, Table Reads and Writes. TABLE 5-2: 8-BIT DE-MULTIPLEXED MODE CONTROL SIGNALS Name 8-bit De-Mux Mode RG0/ALE ...
Page 67
... I/O line, to select between byte and word mode. The other 16-bit modes do not need BA0. JEDEC standard static RAM memories will use the signals for byte selection. 5.3.1 16-BIT BYTE WRITE MODE Figure 5-5 shows an example of 16-bit Byte Write mode for the PIC18C601/801. D<7:0> (MSB) A<19:0> 373 A<x:0> D<15:8> ...
Page 68
... PIC18C601/801 5.3.2 16-BIT WORD WRITE MODE Figure 5-6 shows an example of 16-bit Word Write mode for the PIC18C801. FIGURE 5-6: 16-BIT WORD WRITE MODE EXAMPLE PIC18C801 AD<7:0> AD<15:8> ALE A<19:16> CS1 OE WRH Note 1: This signal only applies to Table Writes. See Section 6.0, Table Reads and Writes. ...
Page 69
... MODE CONTROL SIGNALS Table 5-3 describes the 16-bit mode control signals for the PIC18C601/801. TABLE 5-3: PIC18C601/801 16-BIT MODE CONTROL SIGNALS 18C601 16-bit Name Mode RG0/ALE ALE RG1/OE OE RG2/WRL WRL RG3/WRH WRH RG4/BA0 BA0 RF3/CSIO CSIO RF4/CS2 N/A RF5/CS1 ...
Page 70
... The chip select signals are CS1, CS2 and CSIO. CS1 and CS2 are general purpose chip selects that are used to enable large portions of program mem- ory. CSIO is used to enable external I/O expansion. The PIC18C601uses two of these programmable chip selects: CS1 and CSIO. REGISTER 5-2: CSEL2 REGISTER ...
Page 71
... CS1 ACTIVE 2001 Microchip Technology Inc. PIC18C601/801 A 00h value in the CSEL2 register will disable the CS2 signal and will configure the RF4 pin as I/O. Figure 5-9 shows an example address map for CS2. 5.4.3 CHIP SELECT I/O (CSIO) ...
Page 72
... PIC18C601/801 5.5 External Wait Cycles The external memory interface supports wait cycles. Wait cycles only apply to Table Read and Table Write operations over the external bus. See Section 6.0 for more details. Since the device execution is tied to instruction fetches, there is no need to execute faster than the fetch rate. ...
Page 73
... TABLE READS/TABLE WRITES PIC18C601/801 devices use two memory spaces: the external program memory space and the data memory space. Table Reads and Table Writes have been pro- vided to move data between these two memory spaces through an 8-bit register (TABLAT). The operations that allow the processor to move data ...
Page 74
... PIC18C601/801 6.1 Control Registers Several control registers are used in conjunction with the TBLRD and TBLWT instructions. These include: • TABLAT register • TBLPTR registers 6.1.1 TABLAT - TABLE LATCH REGISTER The Table Latch (TABLAT 8-bit register mapped into the SFR space. The Table Latch is used to hold 8-bit data during data transfers between program mem- ory and data memory ...
Page 75
... Instruction INST(PC-2) Execution 2001 Microchip Technology Inc. PIC18C601/801 Table Reads from external program memory are performed one byte at a time. If the external interface is 8-bit, the bus interface circuitry in TABLAT will load the external value into TABLAT. If the external interface is ...
Page 76
... PIC18C601/801 FIGURE 6-4: TBLRD EXTERNAL INTERFACE TIMING (8-BIT DE-MULTIPLEXED MODE A<15:8> 03AAAh 08h 00h AD<7:0> BA0 ALE OE ’1’ WRH ’1’ WRL Opcode Fetch Memory Cycle TBLRD* from 007554h Instruction INST(PC-2) Execution FIGURE 6-5: TBLRD EXTERNAL BUS TIMING (16-BIT MODE) ...
Page 77
... Table Write Table Write operations store data from the data mem- ory space into external program memory. PIC18C601/801devices perform Table Writes one byte at a time. Table Writes to external memory are two-cycle instructions, unless wait states are enabled. The last cycle writes the data to the external memory location. ...
Page 78
... PIC18C601/801 6.3.1 8-BIT EXTERNAL TABLE WRITES When the external bus is 8-bit, the byte-wide Table Write exactly corresponds to the bus length and there are no special considerations required. The WRL signal is used as the active write signal. Figure 6-6 and Figure 6-7 show the timings associated with the 8-bit modes ...
Page 79
... AD<7:0> BA0 ALE OE ’1’ WRH WRL Memory Opcode Fetch Cycle TBLWT* from 007554h Instruction INST(PC-2) Execution 2001 Microchip Technology Inc. PIC18C601/801 03Ah CCFh 55h 0Eh 92h Opcode Fetch TBLWT 92h MOVLW 55h to 199E67h from 007556h TBLWT Cycle1 ...
Page 80
... PIC18C601/801 6.3.2 16-BIT EXTERNAL TABLE WRITE (BYTE WRITE MODE) This mode allows Table Writes to byte-wide external memories. During a TBLWT cycle, the TABLAT data is presented on the upper and lower byte of the AD<15:0> bus. The appropriate WRH or WRL line is strobed based on the LSb of the TBLPTR. Figure 6-8 shows the timing associated with this mode ...
Page 81
... Figure 6-9 shows the timing associated with this mode 6FF4h 3AACh 000Ch CF33h Opcode Fetch TBLWT 56h to 199E66h TBLWT* from 007558h MOVWF Advance Information PIC18C601/801 CF33h 9256h 3AADh 0E55h Opcode Fetch TBLWT 92h MOVLW 55h to 199E67h from 00755Ah TBLWT* Cycle1 TBLWT* Cycle2 DS39541A-page 81 ...
Page 82
... PIC18C601/801 6.3.4 16-BIT EXTERNAL TABLE WRITE (BYTE SELECT MODE) This mode allows Table Writes to word-wide external memories that have byte selection capabilities. This generally includes word-wide FLASH devices and word-wide static RAM devices. During a TBLWT cycle, the TABLAT data is presented on the upper and lower byte of the AD<15:0> bus. ...
Page 83
... Long Writes Long writes will not be supported on the PIC18C601/801 to program FLASH configuration memory. The configu- ration locations can only be programmed in ICSP mode. 6.5 External Wait Cycles The Table Reads and Writes have the capability to insert wait states when accessing external memory. ...
Page 84
... PIC18C601/801 FIGURE 6-12: EXTERNAL INTERFACE TIMING (16-BIT MODE Apparent Q Actual A<19:16> 0h 3AABh AD<15:0> BA0 ALE OE WRH ’1’ WRL ’1’ Opcode Fetch MOVLW 55h from 007556h DS39541A-page 0Ch 0E55h CF33h Table Read of 92h from 199E67h Advance Information 9256h ’1’ ...
Page 85
... X 8 HARDWARE MULTIPLIER hardware multiplier is included in the ALU of PIC18C601/801 devices. By making the multiply a hardware operation, it completes in a single instruction cycle. This is an unsigned multiply that gives a 16-bit result. The result is stored into the 16-bit product regis- ter pair (PRODH:PRODL). The multiplier does not affect any flags in the STATUS register ...
Page 86
... PIC18C601/801 7.1 Operation Example 7-1 shows the sequence to perform unsigned multiply. Only one instruction is required when one argument of the multiply is already loaded in the WREG register. Example 7-2 shows the sequence signed multiply. To account for the sign bits of the arguments, each argument’s most significant bit (MSb) is tested and the appropriate subtractions are done ...
Page 87
... ARG1 MOVFF ARG1L, WREG ; SUBWF RES2 ; MOVFF ARG1H, WREG ; SUBWFB RES3 ; SIGN_ARG1 BTFSS ARG1H ARG1H:ARG1L neg? GOTO CONT_CODE ; no, done MOVFF ARG2L, WREG ; SUBWF RES2 ; MOVFF ARG2H, WREG ; SUBWFB RES3 ; CONT_CODE : 2001 Microchip Technology Inc. products products Advance Information PIC18C601/801 DS39541A-page 87 ...
Page 88
... PIC18C601/801 NOTES: DS39541A-page 88 Advance Information 2001 Microchip Technology Inc. ...
Page 89
... INTERRUPTS PIC18C601/801 devices have 15 interrupt sources and an interrupt priority feature that allows each interrupt source to be assigned a high priority level low pri- ority level. The high priority interrupt vector is at 000008h and the low priority interrupt vector is at 000018h. High priority interrupt events will override any low priority interrupts that may be in progress ...
Page 90
... PIC18C601/801 FIGURE 8-1: INTERRUPT LOGIC Peripheral Interrupt Flag bit Peripheral Interrupt Enable bit Peripheral Interrupt Priority bit TMR1IF TMR1IE TMR1IP XXXXIF XXXXIE XXXXIP Additional Peripheral Interrupts High Priority Interrupt Generation Low Priority Interrupt Generation Peripheral Interrupt Flag bit Peripheral Interrupt Enable bit ...
Page 91
... User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows software polling. 2001 Microchip Technology Inc. PIC18C601/801 8.1.1 INTCON REGISTERS The INTCON Registers are readable and writable registers, which contain various enable, priority, and flag bits ...
Page 92
... PIC18C601/801 REGISTER 8-2: INTCON2 REGISTER R/W-1 R/W-1 RBPU INTEDG0 bit 7 bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6 INTEDG0: External Interrupt 0 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge ...
Page 93
... Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit, or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows software polling. 2001 Microchip Technology Inc. PIC18C601/801 U-0 R/W-0 R/W-0 — ...
Page 94
... PIC18C601/801 8.1.2 PIR REGISTERS The Peripheral Interrupt Request (PIR) registers con- tain the individual flag bits for the peripheral interrupts (Register 8-5). There are two Peripheral Interrupt Request (Flag) registers (PIR1, PIR2). Note 1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit, or the global enable bit, GIE (INTCON register) ...
Page 95
... Value at POR 2001 Microchip Technology Inc. R/W-0 R-0 R-0 R/W-0 ADIF RCIF TXIF SSPIF W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared Advance Information PIC18C601/801 R/W-0 R/W-0 R/W-0 CCP1IF TMR2IF TMR1IF bit Bit is unknown DS39541A-page 95 ...
Page 96
... PIC18C601/801 REGISTER 8-6: PIR2 REGISTER U-0 — bit 7 bit 7-4 Unimplemented: Read as’0’ bit 3 BCLIF: Bus Collision Interrupt Flag bit bus collision occurred (must be cleared in software bus collision occurred bit 2 LVDIF: Low Voltage Detect Interrupt Flag bit low voltage condition occurred ...
Page 97
... Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Legend Readable bit - n = Value at POR 2001 Microchip Technology Inc. PIC18C601/801 R/W-0 R/W-0 R/W-0 RCIE TXIE SSPIE W = Writable bit U = Unimplemented bit, read as ‘0’ ...
Page 98
... PIC18C601/801 REGISTER 8-8: PIE2 REGISTER U-0 — bit 7 bit 7-4 Unimplemented: Read as '0' bit 3 BCLIE: Bus Collision Interrupt Enable bit 1 = Enabled 0 = Disabled bit 2 LVDIE: Low Voltage Detect Interrupt Enable bit 1 = Enabled 0 = Disabled bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enables the TMR3 overflow interrupt ...
Page 99
... High priority 0 = Low priority bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority Legend Readable bit - n = Value at POR 2001 Microchip Technology Inc. PIC18C601/801 R/W-1 R/W-1 R/W-1 RCIP TXIP SSPIP W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’ ...
Page 100
... PIC18C601/801 REGISTER 8-10: IPR2 REGISTER U-0 — bit 7 bit 7-4 Unimplemented: Read as '0' bit 3 BCLIP: Bus Collision Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 LVDIP: Low Voltage Detect Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit ...
Page 101
... MOVF W_TEMP, W MOVFF STATUS_TEMP, STATUS 2001 Microchip Technology Inc. PIC18C601/801 in the TMR0H:TMR0L registers will set flag bit TMR0IF. The interrupt can be enabled/disabled by setting/clear- ing enable bit TMR0IE (INTCON register). Interrupt prior- ity for Timer0 is determined by the value contained in the interrupt priority bit TMR0IP (INTCON2 register). See Section 10 ...
Page 102
... PIC18C601/801 NOTES: DS39541A-page 102 Advance Information 2001 Microchip Technology Inc. ...
Page 103
... The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs. Note Power-on Reset, PORTA pins RA3:RA0 and RA5 default to analog inputs. 2001 Microchip Technology Inc. PIC18C601/801 EXAMPLE 9-1: CLRF PORTA CLRF LATA MOVLW ...
Page 104
... PIC18C601/801 FIGURE 9-2: RA4/T0CKI PIN BLOCK DIAGRAM RD LATA Data Bus LATA PORTA Data Latch TRISA Schmitt CK Q Trigger Input TRIS Latch Buffer RD TRISA PORTA TMR0 Clock Input Note 1: I/O pin has diode protection to V only. SS TABLE 9-1: PORTA FUNCTIONS Name Bit# ...
Page 105
... RBIF to be cleared. P Pull-up The interrupt-on-change feature is recommended for wake-up on key depression operation and operations (1) I/O pin where PORTB is only used for the interrupt-on-change feature. Polling of PORTB is not recommended while using the interrupt-on-change feature. ST Buffer Q1 RD PORTB Q3 and Advance Information PIC18C601/801 DS39541A-page 105 ...
Page 106
... PIC18C601/801 FIGURE 9-4: RB2:RB0 PINS BLOCK DIAGRAM (2) RBPU Data Latch Data Bus Port CK TRIS Latch TRIS CK RD TRIS Port Schmitt Trigger RBx/INTx Buffer Note 1: I/O pins have diode protection enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2 register). ...
Page 107
... Bit 3 Bit 2 RB5 RB4 RB3 RB2 INT0IE RBIE TMR0IF INT0IF — INT2IE INT1IE — Advance Information PIC18C601/801 Value on Value on Bit 1 Bit 0 all other POR, BOR RESETS RB1 RB0 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 1111 1111 1111 1111 RBIF 0000 000x 0000 000u — ...
Page 108
... PIC18C601/801 9.3 PORTC, TRISC and LATC Registers PORTC is an 8-bit wide, bi-directional port. The corre- sponding data direction register is TRISC. Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a Hi-Impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i ...
Page 109
... LATC LATC Data Output Register TRISC PORTC Data Direction Register Legend unknown unchanged 2001 Microchip Technology Inc. PIC18C601/801 Function Input/output port pin or Timer1 oscillator output or Timer1/Timer3 clock input. Input/output port pin, Timer1 oscillator input. Input/output port pin or Capture1 input/Compare1 output/ PWM1 output. ...
Page 110
... PIC18C601/801 9.4 PORTD, TRISD and LATD Registers PORTD is an 8-bit wide, bi-directional port. The corre- sponding data direction register is TRISD. Setting a TRISD bit (= 1) will make the corresponding PORTD pin an input (i.e., put the corresponding output driver in a Hi-Impedance mode). Clearing a TRISD bit (= 0) will make the corresponding PORTD pin an output (i ...
Page 111
... PORTD BLOCK DIAGRAM IN SYSTEM BUS MODE RD PORTD Data Bus WR LATD or PORTD WR TRISD Bus Enable System Bus Data/TRIS Out Control Drive Bus Instruction Register Note 1: I/O pins have protection diodes to V 2001 Microchip Technology Inc. PIC18C601/801 LATD Port Data 1 CK Data Latch D ...
Page 112
... Legend Schmitt Trigger input, TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in System Bus mode. 2: RDx is used as a multiplexed address/data bus for PIC18C601 and PIC18C801 in 16-bit mode, and as an address only for PIC18C801 in 8-bit mode. ...
Page 113
... RD TRISE Peripheral Enable RD PORTE Peripheral Data In Note 1: I/O pins have diode protection to V 2001 Microchip Technology Inc. PIC18C601/801 byte of the address/data bus (AD15:AD8 the high order address byte (A15:A8), if address and data buses are de-multiplexed. Note: On Power-on Reset, PORTE defaults to the system bus. ...
Page 114
... PIC18C601/801 FIGURE 9-10: PORTE BLOCK DIAGRAM IN SYSTEM BUS MODE RD PORTE Data Bus WR LATE or PORTE WR TRISE External Enable System Bus Data/Address Out Control Drive System To Instruction Register Note 1: I/O pins have diode protection to V DS39541A-page 114 LATD Port Data 1 CK Data Latch ...
Page 115
... Legend Schmitt Trigger input, TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in System Bus mode. 2: REx is used as a multiplexed address/data bus for PIC18C601 and PIC18C801 in 16-bit mode, and as an address only for PIC18C801 in 8-bit mode. ...
Page 116
... CSEL2 and CSELIO registers must set to all zero, to enable these pins as I/O pins, while for PIC18C601 devices, only CSELIO register needs to be set to zero. For PIC18C601 devices, pin RF4 can only be config- ured as I/O when the EBDIS bit is set and execution is taking place in internal Boot RAM. ...
Page 117
... FIGURE 9-13: RF7:RF6 PINS BLOCK DIAGRAM RD PORTF Data Bus WR LATF or PORTF WR TRISF UB/LB Out System Bus WM = ’01’ Control Drive System Note 1: I/O pins have diode protection to V 2001 Microchip Technology Inc. PIC18C601/801 LATF Port Data 1 CK Data Latch TRIS Latch ...
Page 118
... PIC18C601/801 TABLE 9-11: PORTF FUNCTIONS Name Bit# Buffer Type RF0/AN5 bit0 ST RF1/AN6 bit1 ST RF2/AN7 bit2 ST RF3/CSIO bit3 ST (1) RF4/A16/CS2 bit4 ST RF5/CS1 bit5 ST RF6/LB bit6 ST RF7/UB bit7 ST Legend Schmitt Trigger input Note 1: CS2 is available only on PIC18C801. TABLE 9-12: SUMMARY OF REGISTERS ASSOCIATED WITH PORTF ...
Page 119
... Alternate method ; to clear output ; data latches MOVLW 04h ; Value used to ; initialize data ; direction MOVWF TRISG ; Set RG1:RG0 as outputs ; RG2 as input ; RG4:RG3 as outputs 2001 Microchip Technology Inc. PIC18C601/801 FIGURE 9-14: RD LATG Data Bus D WR LATG CK or PORTG Data Latch D WR TRISG CK TRIS Latch ...
Page 120
... PIC18C601/801 FIGURE 9-15: PORTG BLOCK DIAGRAM IN SYSTEM BUS MODE RD PORTG Data Bus WR LATG or PORTG WR TRISG Control Out System Bus External Enable Control Drive System Note 1: I/O pins have diode protection to V TABLE 9-13: PORTG FUNCTIONS Name Bit# Buffer Type RG0/ALE bit0 ...
Page 121
... Note 1: I/O pins have diode protection to V PORTH pins FIGURE 9-17: Data Bus WR LATH or PORTH WR TRISH RD PORTH To A/D Converter Note 1: I/O pins have diode protection to V Advance Information PIC18C601/801 RH3:RH0 PINS BLOCK DIAGRAM IN I/O MODE RD LATH D Q (1) I/O pin CK Data Latch D Q Schmitt CK ...
Page 122
... PIC18C601/801 FIGURE 9-18: RH3:RH0 PINS BLOCK DIAGRAM IN SYSTEM BUS MODE RD PORTH Data Bus WR LATH or PORTH WR TRISH External Enable. System Bus Address Out Control Drive System To Instruction Register Note 1: I/O pins have diode protection to V DS39541A-page 122 LATD Port Data 1 CK Data Latch ...
Page 123
... PGRM WAIT1 Legend unknown unchanged unimplemented. Shaded cells are not used by PORTH. 2001 Microchip Technology Inc. PIC18C601/801 Function Input/output port pin or Address bit 16 for external memory interface Input/output port pin or Address bit 17 for external memory interface Input/output port pin or Address bit 18 for external memory interface ...
Page 124
... PIC18C601/801 9.9 PORTJ, LATJ, and TRISJ Registers Note: PORTJ is available only on PIC18C801 devices. PORTJ is an 8-bit wide, bi-directional I/O port. The cor- responding data direction register is TRISJ. Setting a TRISJ bit (= 1) will make the corresponding PORTJ pin an input (i.e., put the corresponding output driver in a Hi-Impedance mode) ...
Page 125
... PORTJ BLOCK DIAGRAM IN SYSTEM DATA BUS MODE RD PORTJ Data Bus WR LATJ or PORTJ WR TRISJ External Enable System Bus Data Out Control Drive System To Instruction Register Note 1: I/O pins have diode protection to V 2001 Microchip Technology Inc. PIC18C601/801 LATD Port Data 1 CK Data Latch TRIS Latch ...
Page 126
... PIC18C601/801 TABLE 9-17: PORTJ FUNCTIONS Name Bit# Buffer Type (1) RJ0/D0 bit0 ST/TTL (1) RJ1/D1 bit1 ST/TTL (1) RJ2/D2 bit2 ST/TTL (1) RJ3/D3 bit3 ST/TTL (1) RJ4/D4 bit4 ST/TTL (1) RJ5/D5 bit5 ST/TTL (1) RJ6/D6 bit6 ST/TTL (1) RJ7/D7 bit7 ST/TTL Legend Schmitt Trigger input, TTL = TTL input Note 1: PORTJ is available only on PIC18C801 devices. ...
Page 127
... Note: Timer0 is enabled on POR. R/W-1 R/W-1 R/W-1 R/W-1 T08BIT T0CS T0SE W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared Advance Information PIC18C601/801 R/W-1 R/W-1 R/W-1 PSA T0PS2 T0PS1 T0PS0 bit Bit is unknown DS39541A-page 127 ...
Page 128
... PIC18C601/801 FIGURE 10-1: TIMER0 BLOCK DIAGRAM IN 8-BIT MODE OSC 1 RA4/T0CKI (2) pin T0SE (1) T0CS Note 1: Upon RESET, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. 2: I/O pins have diode protection to V FIGURE 10-2: TIMER0 BLOCK DIAGRAM IN 16-BIT MODE OSC ...
Page 129
... Timer0 to be updated at once. Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 RBIE TMR0IF INT0IF T0CS T0SE PSA T0PS2 T0PS1 T0PS0 Advance Information PIC18C601/801 Value on Value on Bit 0 all other POR, BOR RESETS xxxx xxxx uuuu uuuu 0000 0000 0000 0000 RBIF 0000 000x 0000 000u ...
Page 130
... PIC18C601/801 11.0 TIMER1 MODULE The Timer1 module timer/counter has the following features: • 16-bit timer/counter (Two 8-bit registers: TMR1H and TMR1L) • Readable and writable (both registers) • Internal or external clock select • Interrupt on overflow from FFFFh to 0000h • RESET from CCP module special event trigger ...
Page 131
... Timer1 also has an internal “RESET input”. This RESET can be generated by the CCP module (Table 14.0). CCP Special Event Trigger TMR1 CLR TMR1L TMR1ON On/Off T1SYNC 1 T1OSCEN Prescaler Enable OSC (1) Oscillator Internal 0 Clock T1CKPS1:T1CKPS0 TMR1CS Advance Information PIC18C601/801 Synchronized 0 Clock Input 1 Synchronize det 2 SLEEP Input DS39541A-page 131 ...
Page 132
... PIC18C601/801 FIGURE 11-2: TIMER1 BLOCK DIAGRAM: 16-BIT READ/WRITE MODE Data Bus<7:0> 8 TMR1H 8 Write TMR1L Read TMR1L TMR1IF TMR1 8 Overflow Timer 1 Interrupt High Byte Flag bit T1OSC T13CKI/T1OSO T1OSCEN Enable T1OSI Oscillator Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This reduces power drain. ...
Page 133
... TMR1 interrupt, if enabled, is generated on overflow, which is latched in interrupt flag bit TMR1IF (PIR regis- ters). This interrupt can be enabled/disabled by setting/ clearing TMR1 interrupt enable bit TMR1IE (PIE registers). 2001 Microchip Technology Inc. PIC18C601/801 11.4 Resetting Timer1 using a CCP Trigger Output If the CCP module is configured in Compare mode to ...
Page 134
... PIC18C601/801 TABLE 11-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER Name Bit 7 Bit 6 Bit 5 INTCON GIE/ PEIE/ TMR0IE GIEH GIEL PIR1 — ADIF RCIF PIE1 — ADIE RCIE IPR1 — ADIP RCIP TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register ...
Page 135
... Prescaler Prescaler is 16 Legend Readable bit - n = Value at POR 2001 Microchip Technology Inc. PIC18C601/801 12.1 Timer2 Operation Timer2 can be used as the PWM time-base for the PWM mode of the CCP module. The TMR2 register is read- able and writable, and is cleared on any device RESET. ...
Page 136
... PIC18C601/801 12.2 Timer2 Interrupt The Timer2 module has an 8-bit period register, PR2. Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is a readable and writable register. The PR2 register is initialized to FFh upon RESET. FIGURE 12-1: ...
Page 137
... Stops Timer3 Legend Readable bit - n = Value at POR 2001 Microchip Technology Inc. PIC18C601/801 Figure 13 simplified block diagram of the Timer3 module. Register 13-1 shows the Timer3 Control register. This register controls the operating mode of the Timer3 module and sets the CCP clock source. ...
Page 138
... PIC18C601/801 13.1 Timer3 Operation Timer3 can operate in one of these modes: • timer • synchronous counter • asynchronous counter The operating mode is determined by the clock select bit, TMR3CS (T3CON register). FIGURE 13-1: TIMER3 BLOCK DIAGRAM TMR3IF Overflow Interrupt Flag bit TMR3H T1OSC ...
Page 139
... TMR3IF — BCLIE LVDIE TMR3IE — BCLIP LVDIP TMR3IP T1SYNC TMR1CS TMR1ON 0-00 0000 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 Advance Information PIC18C601/801 CCPR1H:CCPR1L registers pair Value on Value on Bit 0 POR, all other BOR RESETS RBIF 0000 000x 0000 000u CCP2IF ---- 0000 ...
Page 140
... PIC18C601/801 NOTES: DS39541A-page 140 Advance Information 2001 Microchip Technology Inc. ...
Page 141
... CCP1M3 U-0 R/W-0 R/W-0 R/W-0 — DC2B1 DC2B0 CCP2M3 W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared Advance Information PIC18C601/801 R/W-0 R/W-0 R/W-0 CCP1M2 CCP1M1 CCP1M0 bit 0 R/W-0 R/W-0 R/W-0 CCP2M2 CCP2M1 CCP2M0 bit 0 ...
Page 142
... PIC18C601/801 14.1 CCP1 Module Capture/Compare/PWM Register1 (CCPR1) is com- prised of two 8-bit registers: CCPR1L (low byte) and CCPR1H (high byte). The CCP1CON register controls the operation of CCP1. All are readable and writable. 14.2 CCP2 Module Capture/Compare/PWM Register2 (CCPR2) is com- prised of two 8-bit registers: CCPR2L (low byte) and CCPR2H (high byte) ...
Page 143
... Q’s Note: I/O pins have diode protection to V 2001 Microchip Technology Inc. PIC18C601/801 Switching from one capture prescaler to another may generate an interrupt. Also, the prescaler counter will not be cleared; therefore, the first capture may be from a non-zero prescaler. Example 14-1 shows the recom- mended method for switching between capture pres- calers ...
Page 144
... PIC18C601/801 14.4 Compare Mode In Compare mode, the 16-bit CCPR1 (CCPR2) register value is constantly compared against either the TMR1 register pair value, or the TMR3 register pair value. When a match occurs, the RC2/CCP1 (RC1/CCP2) pin can have one of the following actions: • Driven high • ...
Page 145
... Holding register for the Most Significant Byte of the 16-bit TMR3 register T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 Legend unknown unchanged unimplemented, read as '0'. Shaded cells are not used by Capture and Timer1. 2001 Microchip Technology Inc. PIC18C601/801 Bit 4 Bit 3 Bit 2 Bit 1 INT0IE RBIE ...
Page 146
... PIC18C601/801 14.5 PWM Mode In Pulse Width Modulation (PWM) mode, the CCP1 pin produces 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with the PORTC data latch, the TRISC<2> bit must be cleared to make the CCP1 pin an output. Note: Clearing the CCP1CON register will force the CCP1 PWM output latch to the default low level ...
Page 147
... Legend unknown unchanged, — = unimplemented, read as '0'. Shaded cells are not used by PWM and Timer2. 2001 Microchip Technology Inc. PIC18C601/801 3. Make the CCP1 pin an output by clearing the TRISC<2> bit. 4. Set the TMR2 prescale value and enable Timer2 by writing to T2CON. ...
Page 148
... PIC18C601/801 NOTES: DS39541A-page 148 Advance Information 2001 Microchip Technology Inc. ...
Page 149
... Serial Peripheral Interface (SPI) 2 • Inter-Integrated Circuit Full Master mode - Slave mode (with general address call) 2 The I C interface supports the following modes in hardware: • Master mode • Multi-Master mode • Slave mode 2001 Microchip Technology Inc. PIC18C601/801 Advance Information DS39541A-page 149 ...
Page 150
... PIC18C601/801 15.2 Control Registers The MSSP module has three associated registers. These include a status register and two control registers. REGISTER 15-1: SSPSTAT REGISTER R/W-0 R/W-0 SMP bit 7 bit 7 SMP: Sample bit SPI Master mode Input data sampled at end of data output time ...
Page 151
... C Slave mode, 7-bit address with START and STOP bit interrupts enabled 2 1111 = I C Slave mode, 10-bit address with START and STOP bit interrupts enabled Legend Readable bit - n = Value at POR 2001 Microchip Technology Inc. PIC18C601/801 R/W-0 R/W-0 R/W-0 SSPEN CKP SSPM3 2 C conditions were not valid for a ...
Page 152
... PIC18C601/801 REGISTER 15-3: SSPCON2 REGISTER R/W-0 R/W-0 GCEN ACKSTAT bit 7 bit 7 GCEN: General Call Enable bit ( Enable interrupt when a general call address (0000h) is received in the SSPSR 0 = General call address disabled bit 6 ACKSTAT: Acknowledge Status bit ( Master Transmit mode Acknowledge was not received from slave ...
Page 153
... Clock edge (output data on rising/falling edge of SCK) • Clock rate (Master mode only) • Slave Select mode (Slave mode only) Figure 15-1 shows the block diagram of the MSSP module, when in SPI mode. 2001 Microchip Technology Inc. PIC18C601/801 FIGURE 15-1: Read SDI SDO SS Control Enable ...
Page 154
... PIC18C601/801 The MSSP consists of a transmit/receive shift register (SSPSR) and a buffer register (SSPBUF). The SSPSR shifts the data in and out of the device, MSb first. The SSPBUF holds the data that was written to the SSPSR, until the received data is ready. Once the 8 bits of data have been received, that byte is moved to the SSPBUF register ...
Page 155
... SSPIF SSPSR to SSPBUF 2001 Microchip Technology Inc. PIC18C601/801 The clock polarity is selected by appropriately program- ming the CKP bit (SSPCON1 register). This, then, would give waveforms for SPI communication as shown in Figure 15-2, Figure 15-4, and Figure 15-5, where the MSb is transmitted first. In Master mode, the ...
Page 156
... PIC18C601/801 15.3.4 SLAVE MODE In Slave mode, the data is transmitted and received as the external clock pulses appear on SCK. When the last bit is latched, the SSPIF interrupt flag bit is set. While in Slave mode, the external clock is supplied by the external clock source on the SCK pin. This external clock must meet the minimum high and low times, as specified in the electrical specifications ...
Page 157
... CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPBUF SDO bit7 SDI (SMP = 0) bit7 Input Sample (SMP = 0) SSPIF SSPSR to SSPBUF 2001 Microchip Technology Inc. PIC18C601/801 bit6 bit5 bit4 bit2 bit3 bit6 bit2 bit5 bit4 bit3 Advance Information bit1 bit0 bit0 Next Q4 Cycle after Q2 bit1 ...
Page 158
... PIC18C601/801 15.3.6 SLEEP OPERATION In Master mode, all module clocks are halted, and the transmission/reception will remain in that state until the device wakes from SLEEP. After the device returns to normal mode, the module will continue to transmit/ receive data. In Slave mode, the SPI transmit/receive shift register operates asynchronously to the device ...
Page 159
... The high and low times of the Addr Match specification, as well as the requirement of the MSSP module, is shown in timing parameter #100 and parameter #101. Set, RESET S, P bits (SSPSTAT reg) and Advance Information PIC18C601/801 2 C oper mode with the SSPEN bit set, DS39541A-page 159 ...
Page 160
... PIC18C601/801 15.4.1.1 Addressing Once the MSSP module has been enabled, it waits for a START condition to occur. Following the START con- dition, the eight bits are shifted into the SSPSR register. All incoming bits are sampled with the rising edge of the clock (SCL) line. The value of register SSPSR<7:1> is compared to the value of the SSPADD register ...
Page 161
... Bit SSPOV is set because the SSPBUF register is still full. R ACK SCL held low while CPU responds to SSPIF Cleared in software SSPBUF is written in software Set bit after writing to SSPBUF (the SSPBUF must be written to before the CKP bit can be set) Advance Information PIC18C601/801 Receiving Data Not ACK Bus Master Terminates Transfer ACK is not sent ...
Page 162
... PIC18C601/801 15.4.2 GENERAL CALL ADDRESS SUPPORT 2 The addressing procedure for the I C bus is such that the first byte after the START condition usually deter- mines which device will be the slave addressed by the master. The exception is the general call address, which can address all devices. When this address is used, all devices should, in theory, respond with an Acknowledge ...
Page 163
... MSSP BLOCK DIAGRAM (I SDA SDA In SCL SCL In Bus Collision Note: I/O pins have diode protection to V 2001 Microchip Technology Inc. PIC18C601/801 1. Assert a START condition on SDA and SCL. 2. Assert a Repeated START condition on SDA and SCL. 3. Write to the SSPBUF register initiating transmis- sion of data/address. ...
Page 164
... PIC18C601/801 2 15.4.4 Master Mode Operation The master device generates all of the serial clock pulses and the START and STOP conditions. A trans- fer is ended with a STOP condition or with a Repeated START condition. Since the Repeated START condi- tion is also the beginning of the next serial transfer, the ...
Page 165
... Set S bit (SSPSTAT) SDA = 1, At completion of START bit, SCL = 1 Hardware clears SEN bit and sets SSPIF bit T T BRG BRG Write to SSPBUF occurs here 1st bit T BRG S Advance Information PIC18C601/801 03h 02h 2 C module is reset into its 2nd bit T BRG DS39541A-page 165 ...
Page 166
... PIC18C601/801 2 15.4 MASTER MODE REPEATED START CONDITION TIMING A Repeated START condition occurs when the RSEN bit (SSPCON2 register) is programmed high and the logic module is in the IDLE state. When the RSEN bit is set, the SCL pin is asserted low. When the SCL pin is sampled low, the baud rate generator is loaded with the contents of SSPADD< ...
Page 167
... In Transmit mode, the BF bit (SSPSTAT register) is set when the CPU writes to SSPBUF, and is cleared when all eight bits are shifted out. 2001 Microchip Technology Inc. PIC18C601/801 15.4.8.2 WCOL Status Flag If the user writes the SSPBUF when a transmit is already in progress (i.e., SSPSR is still shifting out a data byte), the WCOL is set and the contents of the buffer are unchanged (the write doesn’ ...
Page 168
... PIC18C601/801 2 FIGURE 15-15 MASTER MODE WAVEFORM (TRANSMISSION 10-BIT ADDRESS) DS39541A-page 168 Advance Information 2001 Microchip Technology Inc. ...
Page 169
... FIGURE 15-16 MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) 2001 Microchip Technology Inc. PIC18C601/801 Advance Information DS39541A-page 169 ...
Page 170
... PIC18C601/801 15.4.10 ACKNOWLEDGE SEQUENCE TIMING An Acknowledge sequence is enabled by setting the Acknowledge Sequence enable bit, ACKEN (SSPCON2 register). When this bit is set, the SCL pin is pulled low and the contents of the Acknowledge Data bit (ACKDT) is presented on the SDA pin. If the user wishes to gen- erate an Acknowledge, then the ACKDT bit should be cleared ...
Page 171
... Release SCL, Slave device holds SCL low. to measure high time interval SCL SDA T BRG 2001 Microchip Technology Inc. PIC18C601/801 15.4.13 SLEEP OPERATION While in SLEEP mode, the I addresses or data, and when an address match or complete byte transfer occurs, wake the processor from SLEEP (if the MSSP interrupt is enabled). ...
Page 172
... PIC18C601/801 15.4.15 MULTI-MASTER MODE In Multi-Master mode, the interrupt generation on the detection of the START and STOP conditions allows the determination of when the bus is free. The STOP (P) and START (S) bits are cleared from a RESET, or when the MSSP module is disabled. Control of the I bus may be taken when the P bit (SSPSTAT register) is set, or the bus is idle, with both the S and P bits clear ...
Page 173
... SDA = 0, SCL = 1. S SSPIF 2001 Microchip Technology Inc. PIC18C601/801 If the SDA pin is sampled low during this count, the BRG is reset and the SDA line is asserted early (Figure 15-23). If, however, a '1' is sampled on the SDA pin, the SDA pin is asserted low at the end of the BRG count ...
Page 174
... PIC18C601/801 FIGURE 15-22: BUS COLLISION DURING START CONDITION (SCL = 0) SDA Set SEN, enable START SCL sequence if SDA = 1, SCL = 1 SEN SCL = 0 before BRG time-out, Bus collision occurs, set BCLIF BCLIF S ’0’ ’0’ SSPIF FIGURE 15-23: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION Less than T SDA pulled low by other Master ...
Page 175
... Set BCLIF, release SDA and SCL. RSEN S SSPIF 2001 Microchip Technology Inc. PIC18C601/801 reloaded and begins counting. If SDA goes from high to low before the BRG times out, no bus collision occurs because no two masters can assert SDA at exactly the same time. If SCL goes from high to low before the BRG times out and SDA has not already been asserted, a bus collision occurs ...
Page 176
... PIC18C601/801 15.4.16.3 Bus Collision During a STOP Condition Bus collision occurs during a STOP condition if: a) After the SDA pin has been de-asserted and allowed to float high, SDA is sampled low after the BRG has timed out. b) After the SCL pin is de-asserted, SCL is sam- pled low before SDA goes high ...
Page 177
... Receive Status and Control Register (RCSTA). R/W-0 R/W-0 U-0 TX9 TXEN SYNC W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared Advance Information PIC18C601/801 R/W-0 R-1 R/W-0 — BRGH TRMT TX9D bit Bit is unknown DS39541A-page 177 ...
Page 178
... PIC18C601/801 REGISTER 16-2: RCSTA REGISTER R/W-0 R/W-0 SPEN bit 7 bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (Configures RX/DT and TX/CK pins as serial port pins Serial port disabled bit 6 RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception ...
Page 179
... OSC /(4(X+1)) OSC Bit 4 Bit 3 Bit 2 Bit 1 SYNC — BRGH TRMT CREN ADDEN FERR OERR Advance Information PIC18C601/801 /(16(X + 1)) equation can reduce the OSC BRGH = 1 (High Speed) Baud Rate = F /(16(X+1)) OSC NA Value on Value on all Bit 0 POR, other BOR RESETS TX9D 0000 -010 ...
Page 180
... PIC18C601/801 TABLE 16-3: BAUD RATES FOR SYNCHRONOUS MODE F =25 MHz OSC BAUD SPBRG RATE % value (Kbps) KBAUD ERROR KBAUD (decimal 76.8 77.16 +0.47 80 76.92 96 96.15 +0.16 64 96.15 300 297.62 -0.79 20 294.12 500 480.77 -3.85 12 500 HIGH 6250 - 0 5000 LOW 24 ...
Page 181
... MHz 1 MHz SPBRG % % value ERROR KBAUD ERROR (decimal) +0.23 0.30 +0.16 -0.83 46 1.20 +0.16 +1. -2. -2. 15.63 - 255 0.06 Advance Information PIC18C601/801 5.0688 MHz SPBRG SPBRG % value value KBAUD ERROR (decimal) (decimal 1. 2. 9.90 +3. 19.80 +3. 79.20 +3. 79. 255 0.31 - 255 32 ...
Page 182
... PIC18C601/801 TABLE 16-5: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = MHz OSC BAUD SPBRG RATE % value (Kbps) KBAUD ERROR KBAUD (decimal 9.6 9.59 -0.15 162 19.2 19.30 +0.47 80 76.8 78.13 +1. 97.66 +1.73 15 300 312.50 +4.17 4 312.50 500 520.83 +4.17 2 HIGH 1562.50 ...
Page 183
... TX9D. 7. Load data to the TXREG register (starts trans- mission). Data Bus TXREG Register 8 MSb LSb (8) 0 TSR Register TRMT TX9 TX9D and Advance Information PIC18C601/801 ), the TXREG register is CY Pin Buffer and Control RC6/TX/CK pin SPEN DS39541A-page 183 ...
Page 184
... PIC18C601/801 FIGURE 16-2: ASYNCHRONOUS TRANSMISSION Write to TXREG Word 1 BRG Output (Shift Clock) RC6/TX/CK (pin) START Bit TXIF bit (Transmit Buffer Register Empty Flag) Word 1 TRMT bit Transmit Shift Reg (Transmit Shift Register Empty Flag) FIGURE 16-3: ASYNCHRONOUS TRANSMISSION (BACK TO BACK) Write to TXREG ...
Page 185
... Pin Buffer and Control SPEN Note: I/O pins have diode protection to V 2001 Microchip Technology Inc. PIC18C601/801 16.2.3 SETTING UP 9-BIT MODE WITH ADDRESS DETECT This mode would typically be used in RS-485 systems. Steps to follow when setting up an Asynchronous Reception with Address Detect Enable: 1 ...
Page 186
... PIC18C601/801 FIGURE 16-5: ASYNCHRONOUS RECEPTION START RX (pin) bit bit0 bit1 Rcv Shift Reg Rcv Buffer Reg Read Rcv Buffer Reg RCREG RCIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set ...
Page 187
... Baud Rate Generator Register Legend unknown unimplemented, read as '0'. Shaded cells are not used for Synchronous Master Transmission. 2001 Microchip Technology Inc. PIC18C601/801 bit TXIF (PIR registers) is set. The interrupt can be enabled/disabled by setting/clearing enable bit TXIE (PIE registers). Flag bit TXIF will be set, regardless of the state of enable bit TXIE, and cannot be cleared in software ...
Page 188
... PIC18C601/801 FIGURE 16-6: SYNCHRONOUS TRANSMISSION RC7/RX/DT Bit 0 pin RC6/TX/CK pin Write to TXREG Reg Write Word 1 Write Word 2 TXIF bit (Interrupt Flag) TRMT TRMT bit ’1’ TXEN bit Note: Sync Master mode; SPBRG = ’0’; continuous transmission of two 8-bit words. FIGURE 16-7: ...
Page 189
... RCIF bit (interrupt) Read RXREG Note: Timing diagram demonstrates SYNC Master mode with bit SREN = ’1’ and bit BRGH = ’0’. 2001 Microchip Technology Inc. PIC18C601/801 3. Ensure bits CREN and SREN are clear interrupts are desired, set enable bit RCIE. 5. ...
Page 190
... PIC18C601/801 16.4 USART Synchronous Slave Mode Synchronous Slave mode differs from the Master mode, in that the shift clock is supplied externally at the RC6/TX/CK pin (instead of being supplied internally in Master mode). This allows the device to transfer or receive data while in SLEEP mode. Slave mode is entered by clearing bit CSRC (TXSTA register) ...
Page 191
... RCREG USART Receive Register TXSTA CSRC TX9 TXEN SPBRG Baud Rate Generator Register Legend unknown unimplemented, read as '0'. Shaded cells are not used for Synchronous Slave Reception. 2001 Microchip Technology Inc. PIC18C601/801 Bit 4 Bit 3 Bit 2 Bit 1 INT0IE RBIE TMR0IF INT0IF TXIF ...
Page 192
... PIC18C601/801 NOTES: DS39541A-page 192 Advance Information 2001 Microchip Technology Inc. ...
Page 193
... ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE The analog-to-digital (A/D) converter module has 8 inputs for the PIC18C601 devices and 12 for the PIC18C801 devices. This module has the ADCON0, ADCON1, and ADCON2 registers. The A/D allows conversion of an analog input signal to a corresponding 10-bit digital number. ...
Page 194
... PIC18C601/801 REGISTER 17-2: ADCON1 REGISTER U-0 — bit 7 bit 7-6 Unimplemented: Read as '0' bit 5-4 VCFG1:VCFG0: Voltage Reference Configuration bits 00 External External V 11 bit 3-0 PCFG3:PCFG0: A/D Port Configuration Control bits AN11 AN10 AN9 A 0000 A 0001 A 0010 A 0011 D 0100 D 0101 D 0110 ...
Page 195
... A/D conversion. When the A/D conver- sion is complete, the result is loaded into the ADRESH/ADRESL registers, the GO/DONE bit (ADCON0 register) is cleared, and A/D interrupt flag bit ADIF is set. The block diagram of the A/D module is shown in Figure 17-1. Advance Information PIC18C601/801 R/W-0 R/W-0 R/W-0 ADCS2 ADCS1 ADCS0 ...
Page 196
... PIC18C601/801 FIGURE 17-1: A/D BLOCK DIAGRAM A/D Converter V REF (Reference Voltage REF (Reference Voltage) Note 1: These channels are not available on the PIC18C601 devices. DS39541A-page 196 CHS3:CHS0 V IN (Input voltage VCFG0 AV SS VCFG1 Advance Information 0111 RF2/AN7 0110 RF1/AN6 0101 RF0/AN5 0100 ...
Page 197
... R = interconnect resistance sampling switch C = sample/hold capacitance (from DAC) HOLD R = sampling switch resistance SS 2001 Microchip Technology Inc. PIC18C601/801 2. Configure A/D interrupt (if desired): • Clear ADIF bit • Set ADIE bit • Set GIE bit 3. Wait the required acquisition time. 4. Start conversion: • ...
Page 198
... PIC18C601/801 17.1 A/D Acquisition Requirements For the A/D converter to meet its specified accuracy, the charge holding capacitor (C ) must be allowed HOLD to fully charge to the input channel voltage level. The analog input model is shown in Figure 17-2. The source impedance (R ) and the internal sampling ...
Page 199
... AD 2: Analog levels on any pin defined as a dig- ital input may cause the input buffer to consume current out of the device’s spec- ification limits. ) Maximum Device Frequency PIC18C601/801 1.25 MHz 000 2.50 MHz 100 5.00 MHz 001 10.0 MHz 101 20 ...
Page 200
... PIC18C601/801 17.4 A/D Conversions Figure 17-3 shows the operation of the A/D converter after the GO bit has been set. Clearing the GO/DONE bit during a conversion will abort the current conver- sion. The A/D result register pair will NOT be updated with the partially completed A/D conversion sample. ...