PIC18F4320-E/PT Microchip Technology, PIC18F4320-E/PT Datasheet - Page 121
![IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,44PIN,PLASTIC](/photos/6/82/68251/c04-076_pt_sml.jpg)
PIC18F4320-E/PT
Manufacturer Part Number
PIC18F4320-E/PT
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,44PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16C770-ISO.pdf
(8 pages)
3.PIC18F1320-ISS.pdf
(36 pages)
4.PIC18F2220-ISO.pdf
(394 pages)
5.PIC18F2220-ISO.pdf
(6 pages)
6.PIC18F2220-ISO.pdf
(6 pages)
7.PIC18F2220-ISO.pdf
(8 pages)
8.PIC18F2220-ISO.pdf
(6 pages)
9.PIC18F2220-ISO.pdf
(6 pages)
Specifications of PIC18F4320-E/PT
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
36
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F4320-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC16C770-ISO PDF datasheet #2
- PIC18F1320-ISS PDF datasheet #3
- PIC18F2220-ISO PDF datasheet #4
- PIC18F2220-ISO PDF datasheet #5
- PIC18F2220-ISO PDF datasheet #6
- PIC18F2220-ISO PDF datasheet #7
- PIC18F2220-ISO PDF datasheet #8
- PIC18F2220-ISO PDF datasheet #9
- Current page: 121 of 394
- Download datasheet (7Mb)
11.1
Timer0 can operate as a timer or as a counter.
Timer mode is selected by clearing the T0CS bit. In
Timer mode, the Timer0 module will increment every
instruction cycle (without prescaler). If the TMR0 regis-
ter is written, the increment is inhibited for the following
two instruction cycles. The user can work around this
by writing an adjusted value to the TMR0 register.
Counter mode is selected by setting the T0CS bit. In
Counter mode, Timer0 will increment, either on every
rising or falling edge of pin RA4/T0CKI/C1OUT. The
incrementing edge is determined by the Timer0 Source
Edge Select bit (T0SE). Clearing the T0SE bit selects
the rising edge.
When an external clock input is used for Timer0, it must
meet certain requirements. The requirements ensure
the external clock can be synchronized with the internal
phase clock (T
incrementing of Timer0 after synchronization.
11.2
An 8-bit counter is available as a prescaler for the Timer0
module. The prescaler is not readable or writable.
The PSA and T0PS2:T0PS0 bits determine the
prescaler assignment and prescale ratio.
Clearing bit PSA will assign the prescaler to the Timer0
module. When the prescaler is assigned to the Timer0
module, prescale values of 1:2, 1:4,..., 1:256 are
selectable.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF TMR0, MOVWF
TMR0, BSF TMR0, x....etc.) will clear the prescaler
count.
TABLE 11-1:
© 2007 Microchip Technology Inc.
TMR0L
TMR0H
INTCON
T0CON
TRISA
Legend:
Note 1:
Note:
Name
Timer0 Operation
Prescaler
Timer0 Low Byte Register
Timer0 High Byte Register
x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by Timer0.
RA6 and RA7 are enabled as I/O pins depending on the oscillator mode selected in Configuration Word 1H.
Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler
count but will not change the prescaler
assignment.
GIE/GIEH
TMR0ON
RA7
Bit 7
OSC
(1)
REGISTERS ASSOCIATED WITH TIMER0
). Also, there is a delay in the actual
PEIE/GIEL
T08BIT
RA6
Bit 6
(1)
PORTA Data Direction Register
TMR0IE
T0CS
Bit 5
PIC18F2220/2320/4220/4320
INT0IE
T0SE
Bit 4
RBIE
Bit 3
PSA
11.2.1
The prescaler assignment is fully under software
control (i.e., it can be changed “on-the-fly” during
program execution).
11.3
The TMR0 interrupt is generated when the TMR0
register overflows from FFh to 00h in 8-bit mode, or
FFFFh to 0000h in 16-bit mode. This overflow sets the
TMR0IF bit. The interrupt can be masked by clearing
the TMR0IE bit. The TMR0IF bit must be cleared in
software by the Timer0 module Interrupt Service
Routine before re-enabling this interrupt. The TMR0
interrupt cannot awaken the processor from Sleep
mode, since the timer requires clock cycles, even when
T0CS is set.
11.4
TMR0H is not the high byte of the timer/counter in
16-bit mode but is actually a buffered version of the
high byte of Timer0 (refer to Figure 11-2). The high byte
of the Timer0 counter/timer is not directly readable nor
writable. TMR0H is updated with the contents of the
high byte of Timer0 during a read of TMR0L. This pro-
vides the ability to read all 16 bits of Timer0, without
having to verify that the read of the high and low byte
were valid, due to a rollover between successive reads
of the high and low byte.
A write to the high byte of Timer0 must also take place
through the TMR0H Buffer register. Timer0 high byte is
updated with the contents of TMR0H when a write
occurs to TMR0L. This allows all 16 bits of Timer0 to be
updated at once.
TMR0IF
T0PS2
Bit 2
Timer0 Interrupt
16-Bit Mode Timer Reads and
Writes
INT0IF
T0PS1
Bit 1
SWITCHING PRESCALER
ASSIGNMENT
T0PS0
Bit 0
RBIF
xxxx xxxx
0000 0000
0000 000x
1111 1111
1111 1111
POR, BOR
Value on
DS39599G-page 119
uuuu uuuu
0000 0000
0000 000u
1111 1111
1111 1111
Value on
all other
Resets
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