PIC18LF1330-I/ML Microchip Technology, PIC18LF1330-I/ML Datasheet - Page 128
![Microcontroller](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC18LF1330-I/ML
Manufacturer Part Number
PIC18LF1330-I/ML
Description
Microcontroller
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.AC162078.pdf
(318 pages)
3.PIC18F1230-ISO.pdf
(6 pages)
4.PIC18F1230-ISO.pdf
(12 pages)
5.PIC18F1230-ISO.pdf
(4 pages)
Specifications of PIC18LF1330-I/ML
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
16
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- AC162078 PDF datasheet #2
- PIC18F1230-ISO PDF datasheet #3
- PIC18F1230-ISO PDF datasheet #4
- PIC18F1230-ISO PDF datasheet #5
- Current page: 128 of 318
- Download datasheet (3Mb)
PIC18F1230/1330
14.4.4
This mode is available in Continuous Up/Down Count
mode. In the Double Update mode (PTMOD<1:0> = 11),
an interrupt event is generated each time the PTMR
register is equal to zero and each time the PTMR
matches the PTPER register. Figure 14-8 shows the
interrupts in Continuous Up/Down Count mode with
double updates.
The Double Update mode provides two additional
functions to the user in Center-Aligned mode.
1.
FIGURE 14-8:
DS39758D-page 128
Note 1: Interrupt flag bit, PTIF, is sampled here (every Q1).
PTMR_INT_REQ
PTMR_INT_REQ
A: PRESCALER = 1:1
The control loop bandwidth is doubled because
the PWM duty cycles can be updated twice per
period.
2: PWM Time Base Period register, PTPER, is loaded with the value 3FFh for this example.
PTDIR bit
PTDIR bit
PTIF bit
PTIF bit
PTMR
PTMR
OSC1
OSC1
INTERRUPTS IN DOUBLE UPDATE
MODE
Case 1: PTMR Counting Upwards
Case 2: PTMR Counting Downwards
Q1
Q1
1
1
Q2
Q2
PWM TIME BASE INTERRUPTS, CONTINUOUS UP/DOWN COUNT MODE WITH
DOUBLE UPDATES
3FDh
002h
Q3
Q3
Q4
Q4
Q1
Q1
1
1
Q2
Q2
3FEh
001h
Q3
Q3
Q4
Q4
Q1
Q1
1
1
2
Q2
Q2
2.
000h
3FFh
Note:
Q3
Q3
Asymmetrical center-aligned PWM waveforms
can be generated, which are useful for
minimizing output waveform distortion in certain
motor control applications.
Q4
Q4
Do not change the PTMOD bits while
PTEN is active. It will yield unexpected
results. To change the PWM Timer mode
of operation, first clear the PTEN bit, load
PTMOD bits with required data and then
set PTEN.
Q1
Q1
1
1
Q2
Q2
3FEh
001h
Q3
Q3
2009 Microchip Technology Inc.
Q4
Q4
Q1
Q1
Q2
Q2
3FDh
002h
Q3
Q3
Q4
Q4
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