PIC18LF1330-I/ML Microchip Technology, PIC18LF1330-I/ML Datasheet - Page 289
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PIC18LF1330-I/ML
Manufacturer Part Number
PIC18LF1330-I/ML
Description
Microcontroller
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.AC162078.pdf
(318 pages)
3.PIC18F1230-ISO.pdf
(6 pages)
4.PIC18F1230-ISO.pdf
(12 pages)
5.PIC18F1230-ISO.pdf
(4 pages)
Specifications of PIC18LF1330-I/ML
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
16
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- AC162078 PDF datasheet #2
- PIC18F1230-ISO PDF datasheet #3
- PIC18F1230-ISO PDF datasheet #4
- PIC18F1230-ISO PDF datasheet #5
- Current page: 289 of 318
- Download datasheet (3Mb)
FIGURE 23-8:
FIGURE 23-9:
TABLE 23-10: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
2009 Microchip Technology Inc.
Param.
30
31
32
33
34
35
36
37
38
39
No.
Note:
Watchdog
Oscillator
Time-out
Time-out
I/O pins
Internal
Internal
PWRT
MCLR
Reset
Timer
Reset
Internal Reference
Reference Voltage
TmcL
T
T
T
T
T
T
T
T
T
POR
Symbol
V
OST
CSD
WDT
PWRT
IOZ
BOR
IRVST
LVD
IOBST
DD
Enable Internal
Voltage Stable
Refer to Figure 23-5 for load conditions.
AND BROWN-OUT RESET REQUIREMENTS
MCLR Pulse Width (low)
Watchdog Timer Time-out Period
(no postscaler)
Oscillation Start-up Timer Period
Power-up Timer Period
I/O High-Impedance from MCLR
Low or Watchdog Timer Reset
Brown-out Reset Pulse Width
Time for Internal Reference
Voltage to become Stable
Low-Voltage Detect Pulse Width
CPU Start-up Time
Time for INTOSC to Stabilize
V
IRVST
V
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND
POWER-UP TIMER TIMING
BROWN-OUT RESET TIMING
DD
33
Characteristic
32
36
BV
1024 T
DD
55.6
Min
200
200
3.4
—
—
—
—
2
OSC
34
65.5
30
Typ
4.0
20
10
—
—
—
—
2
1
PIC18F1230/1330
1024 T
35
Max
4.6
50
—
75
—
—
—
—
—
OSC
31
Units
ms
ms
s
—
s
s
s
s
s
s
T
V
V
OSC
DD
DD
DS39758D-page 289
B
34
V
= OSC1 period
Conditions
VDD
LVD
(see D005)
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