CV500II101 Omron, CV500II101 Datasheet - Page 159

• Manufacturer Part Number: CV500II101
• Description: Programmable Logic Controller
• Manufacturer: Omron

Specifications of CV500II101

• Peak Reflow Compatible (260 C): No
• Leaded Process Compatible: No
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Alphabetic List of Instructions by Mnemonics
154
Note Instructions with one asterisk (*) are supported by the CVM1D and version-2 CVM1 CPU Units only.
DMPX(j)
DOWN*
DVB(j)
DVBL(j)
ELSE*
EMBC(j)
END
EQU(j)
EXIT(NOT)* <006>
EXP(j)*
FAL(j)
FALS(j)
FDIV(j)
FIFO(j)
FILP(j)***
FILR(j)***
FILW(j)***
FIX(j)*
FIXL(j)*
FLSP(j)***
FLT(j)*
FLTL(j)*
FPD*
HEX(j)*
HMS(j)
IEND*
IF(NOT)*
IL
ILC
INBL(j)
INC(j)
INCB(j)
INCL(j)
IODP(j)
IORF(j)
IORS
IOSP(j)
JME
JMP
KEEP(!)
Mnemonic
Instructions with two asterisks (**) are supported by the CV500, CV1000, and CV2000 only.
Instructions with three asterisks (***) are not supported by the CVM1D.
111
019
083
087
<003>
171
001
025
467
006
007
141
163
182
180
181
450
451
183
452
453
177
117
144
<004>
<002>
002
003
096
090
092
094
189
184
188
187
005
004
011
Code
16-TO-4/256-8 ENCODER
CONDITION OFF
BINARY DIVIDE
DOUBLE BINARY DIVIDE
NO CONDITIONAL BRANCH
SELECT EM BANK
END
EQUAL
CONDITIONAL END
EXPONENT
FAILURE ALARM
FAILURE ALARM
FLOATING POINT
DIVIDE(BCD)
FIRST IN FIRST OUT
READ PROGRAM FILE
READ DATA FILE
WRITE DATA FILE
FLOATING-TO-16-BIT
FLOATING-TO-32-BIT
CHANGE STEP PROGRAM
16-BIT-TO-FLOATING
32-BIT-TO-FLOATING
FAILURE POINT DETECTION
ASCII-TO-HEX
SECONDS-TO-HOURS
END OF BRANCH
CONDITIONAL BRANCH
INTERLOCK
INTERLOCK CLEAR
DOUBLE INCREMENT BINARY
INCREMENT BCD
INCREMENT BINARY
DOUBLE INCREMENT BCD
I/O DISPLAY
I/O REFRESH
ENABLE ACCESS
DISABLE ACCESS
JUMP END
JUMP
KEEP
Name
LEND(NOT)
*
LIFO(j)
LINE(j)
LMT(j)*
LOG(j)*
LOOP*
MARK
MAX(j)
MCMP(j)
MCRO(j)*
MIN(j)
MLB(j)
MLBL(j)
MLPX(j)
MOV(!j)
MOVB(j)
MOVD(j)
MOVL(j)
MOVQ
MOVR(j)
MSG(j)
MSKR(j)*** 155
MSKS(j)*** 153
MTIM
MUL(j)
MULL(j)
MVN(j)
MVNL(j)
NASL(j)*
NASR(j)*
NEG(j)
NEGL(j)
NOP
NOT
NSFL(j)*
NSFR(j)*
NSLL(j)*
NSRL(j)*
ORW(j)
ORWL(j)
PID*
PUSH(j)
Mnemonic
<010>
162
115
271
468
<009>
174
165
024
156
166
082
086
110
030
042
043
032
037
036
195
122
072
076
031
033
056
057
104
105
000
010
054
055
058
059
131
135
270
161
Code
REPEAT BLOCK END
LAST IN FIRST OUT
COLUMN-TO-LINE
LIMIT CONTROL
LOGARITHM
REPEAT BLOCK
MARK TRACE
FIND MAXIMUM
MULTIPLE COMPARE
MACRO
FIND MINIMUM
BINARY MULTIPLY
DOUBLE BINARY MULTIPLY
4-TO-16/8-TO-256 DECODER
MOVE
MOVE BIT
MOVE DIGIT
DOUBLE MOVE
MOVE QUICK
MOVE TO REGISTER
MESSAGE
READ MASK
INTERRUPT MASK
MULTI-OUTPUT TIMER
BCD MULTIPLY
DOUBLE BCD MULTIPLY
MOVE NOT
DOUBLE MOVE NOT
SHIFT N-BITS LEFT
SHIFT N-BITS RIGHT
2’S COMPLEMENT
DOUBLE 2’S COMPLEMENT
NO OPERATION
NOT
SHIFT N-BIT DATA LEFT
SHIFT N-BIT DATA RIGHT
DOUBLE SHIFT N-BIT LEFT
DOUBLE SHIFT N-BIT RIGHT
LOGICAL OR
DOUBLE LOGICAL OR
PID CONTROL
PUSH ONTO STACK
Name
Appendix F