HBCU-5710R Avago Technologies US Inc., HBCU-5710R Datasheet - Page 17

• Manufacturer Part Number: HBCU-5710R
• Description: Fiber Optic Transceiver,Module
• Manufacturer: Avago Technologies US Inc.

Specifications of HBCU-5710R

• Data Rate: 1.25Gbps
• Wavelength: 850nm
• Voltage - Supply: 3.3V
• Connector Type: RJ45
• Mounting Type: Through Hole
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Applications: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 516-2009

Table 13: Register 10 (MASTER-SLAVE Status)
Table 14: Register 16 (Extended Control 1)
17
Bit
Bit
16.15:7
R/W
16.6:5
R/W
16.4:0
R/W
10.15
RO/LH/SC
10.14
RO
10.13
RO
10.12
RO
10.11
RO
10.10
RO
10.9:8
10.7:0
RO/SC
Name
N/A to SFP Module
MDI Crossover Mode
N/A to SFP Module
Name
MASTER-SLAVE Con-
figuration Fault
MASTER-SLAVE Con-
figuration Resolution
Local Receiver Status
Remote Receiver Status
Link Partner Full Duplex
Link Partner Half
Duplex
N/A to SFP Module
Idle Error Count
Description
00 = Manual MDI configuration
01 = Manual MDIX configuration
10 = N/A to SFP module
11 = Enable automatic crossover
Description
1 = MASTER-SLAVE configuration
fault detected
0 = No MASTER-SLAVE configuration
fault detected
1 = Local PHY configuration resolved
to MASTER
0 = Local PHY configuration resolved
to SLAVE
1 = Local Receiver OK
0 = Local Receiver not OK
1 = Remote Receiver OK
0 = Remote Receiver not OK
1 = Link Partner is capable of
1000BASE-T full duplex
0 = Link Parnter is not capable of
1000BASE-T full duplex
1 = Link Partner is capable of
1000BASE-T half duplex
0 = Link Parnter is not capable of
1000BASE-T half duplex
Counts errors when receiving idle
patterns.
Hardware
Reset
0
0
0
0
0
0
00
00000000
Hardware
Reset
000000000
11
11000
Software
Reset
0
0
0
0
0
0
00
00000000
Software
Reset
Retain (15:10,
7) or Update
(9:8)
Update
Retain (2:0) or
Update (4:3)
Details
This bit is cleared each time that
this register is read. This bit clears
on Auto-Negotiation enable or
Auto-Negotiation complete.
This bit is set if the number of
failed MASTER-SLAVE resolutions
reaches 7. This bit is set if both
PHY’s are forced to MASTER’s or
SLAVE’s at the same time using
bits 9.12 and 9.11.
This bit is valid only when the
Page Received bit (6.1) is set to 1.
This bit is valid only when the
Page Received bit (6.1) is set to 1.
These bits do not roll-over when
they are all one’s.
Details
When writing to register 16,
be sure to preserve the values
of these bits. Changes to these
values can interrupt the normal
operation of the SFP module.
Changes to this bit take effect
after software reset.
When writing to register 16,
be sure to preserve the values
of these bits. Changes to these
values can interrupt the normal
operation of the SFP module.