IP-CIC Altera, IP-CIC Datasheet

IP CORE - CIC Compiler

IP-CIC

Manufacturer Part Number
IP-CIC
Description
IP CORE - CIC Compiler
Manufacturer
Altera
Datasheet

Specifications of IP-CIC

Software Application
IP CORE, DSP Filters And Transforms
Supported Families
Arria GX, Cyclone, HardCopy, Stratix, Stratix II
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Lead Free Status / RoHS Status
na
101 Innovation Drive
San Jose, CA 95134
www.altera.com
CIC MegaCore Function
Software Version:
Document Date:
User Guide
December 2010
10.1

Related parts for IP-CIC

IP-CIC Summary of contents

Page 1

... Innovation Drive San Jose, CA 95134 www.altera.com CIC MegaCore Function User Guide Software Version: Document Date: 10.1 December 2010 ...

Page 2

... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation ...

Page 3

... Output Rounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–4 Hogenauer Pruning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–4 Multi-Channel Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–4 Multiple Input Single Output (MISO 4–5 Single Input Multiple Output (SIMO 4–6 Variable Rate Change Factors for Decimation and Interpolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–7 FIR Filter Compensation Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–7 Avalon Streaming Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–9 Avalon-ST Interface Data Transfer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–11 Packet Data Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4– ...

Page 4

... CIC MegaCore Function User Guide Contents © December 2010 Altera Corporation ...

Page 5

... HardCopy device family. The IP core meets all functional and timing requirements for the device family and can be used in production designs. CIC MegaCore ® ® Description 10.1 December 2010 IP-CIC 00BB 6AF7 II software compiles the ® CIC MegaCore Function User Guide ...

Page 6

... Single clock domain with selectable number of interfaces and a maximum of 1,024 channels. ■ Selectable data storage options with an option to use pipelined integrators. ■ Configurable input data width ( bits) and output data width (1 to full resolution data width). ■ Selectable output rounding modes (truncation, convergent rounding, rounding up, or saturation) and Hogenauer pruning support ...

Page 7

... CIC filters use only adders and registers, and require no multipliers to handle large rate changes. Therefore, CIC is a suitable and economical filter architecture for hardware implementation, and is widely used in sample rate conversion designs such as digital down converters (DDC) and digital up converters (DUC) ...

Page 8

... Performance and Resource Utilization (3) f MAX ALUTs (MHz) — 288 16 502 — 312 16 526 — 304 16 509 — 292 16 470 — 268 8 74 492 — 261 12 459 — 302 16 509 — 283 6 90 486 — 188 16 345 . © December 2010 Altera Corporation ...

Page 9

... CIC MegaCore function, where <path> is the installation directory for the Quartus II software. Figure 1–1. Directory Structure <path> Installation directory. ip Contains the Altera MegaCore IP Library and third-party IP cores. altera Contains the Altera MegaCore IP Library. common Contains shared components. cic Contains the CIC MegaCore function files. The default installation directory on Windows is c:\altera\< ...

Page 10

... The untethered time-out for the CIC MegaCore function is one hour; the tethered time-out value is indefinite. The data output signal is forced to zero when the hardware evaluation time expires. CIC MegaCore Function User Guide Chapter 1: About This MegaCore Function Installation and Licensing Megafunctions. © December 2010 Altera Corporation ...

Page 11

... In DSP Builder, a Simulink symbol for the MegaCore function appears in the MegaCore Functions library of the Altera DSP Builder Blockset in the Simulink library browser. You can use the CIC MegaCore function in the MATLAB/Simulink environment by performing the following steps: 1 ...

Page 12

... Click Next and select CIC <version> from the DSP>Filters section in the Installed Plug-Ins tab. CIC MegaCore Function User Guide DSP Builder User Guide. (Figure 2–2 on page 2–3). Chapter 2: Getting Started MegaWizard Plug-In Manager Flow Memory-Mapped ® Avalon Interface (Figure 2–1). © December 2010 Altera Corporation ...

Page 13

... MegaWizard interface to specify the required parameters for the MegaCore function variation. For an example of setting parameters for the CIC MegaCore function, refer to 7. Click Next to complete the parameterization and display the EDA page (Figure 2–3 on page © December 2010 Altera Corporation Chapter 3, Parameter Settings. 2–4). 2–3 ...

Page 14

... Figure 2–3. EDA Page 8. On the EDA page, turn on Generate Simulation Model functional simulation model is a cycle-accurate VHDL or Verilog HDL model produced by the Quartus II software. c Use the simulation models only for simulation and not for synthesis or any other purposes. Using these models for synthesis creates a non-functional design ...

Page 15

... All other files are optional. 12. Click Finish to generate the MegaCore function and supporting files. The generation phase may take several minutes to complete. The generation progress and status is displayed in a report window. © December 2010 Altera Corporation (Figure 2–4). CIC MegaCore Function User Guide 2–5 ...

Page 16

... Click Exit to close the progress report window. Then click Yes on the Quartus II IP Files prompt to add the .qip file describing your custom MegaCore function variation to the current Quartus II project. f Refer to the Quartus II Help for more information about the MegaWizard Plug-In Manager ...

Page 17

... Tools menu in the Quartus II software the Processing menu, point to Start and click Start Analysis & Elaboration the Tools menu, click Tcl scripts. In the Tcl Scripts dialog box, select the <variation name>_nativelink.tcl Tcl script and click Run. Check for a message confirming that the Tcl script was successfully loaded. © ...

Page 18

... Quartus II Handbook. Compile the Design and Program a Device You can use the Quartus II software to compile your design. After a successful compilation, you can program the targeted Altera device and verify the design in hardware. f For instructions on compiling and programming your design, and more information about the MegaWizard Plug-In Manager flow, refer to the Quartus II Help ...

Page 19

... RAM type of integrator data storage Differentiator data storage RAM type of differentiator data storage Use pipelined integrators Number of pipeline stages per integrator 1 If you enable the variable rate change factor option you can also specify minimum and maximum values instead of specifying an actual rate change factor ...

Page 20

... Figure 3–1. Architecture Page CIC MegaCore Function User Guide Chapter 3: Parameter Settings Parameter Setting Examples © December 2010 Altera Corporation ...

Page 21

... Signal Compiler if you are using the DSP Builder flow, or the New Project Wizard if you are using the MegaWizard Plug-In Manager flow. 2. Click Next to display the Parameter Settings: Input/Output Options page (Figure 3–2). Figure 3–2. Input/Output Options Page © December 2010 Altera Corporation 3–3 CIC MegaCore Function User Guide ...

Page 22

... Output data width Output rounding options Apply Hogenauer pruning across filter stages For more information about these parameters, refer to Parameter Descriptions This section describes the CIC MegaCore function parameters, which can be set in the MegaWizard interface (Refer to Table 3–3 shows the parameters that can be set in the Architecture page. ...

Page 23

... Refer to “Output Rounding” on page 4–4 © December 2010 Altera Corporation Turn on to use pipelined integrators. This option is available when the Number of channels per interface is greater than or equal to 2 (or greater than or equal to 6, when the Memory option is selected for integrator data storage). ...

Page 24

... CIC MegaCore Function User Guide Chapter 3: Parameter Settings Parameter Descriptions © December 2010 Altera Corporation ...

Page 25

... The key advantage of CIC filters is that they use only adders and registers, and do not require multipliers to implement in hardware for handling large rate changes. A CIC filter (also known as a Hogenauer filter) can be used to perform either decimation or interpolation ...

Page 26

... CIC decimation filter with and R = 32. Figure 4–5. Three stage CIC Decimation Filter Frequency Response CIC MegaCore Function User Guide Low Sampling Frequency Differentiator Section High Sampling Frequency Integrator Section Chapter 4: Functional Description Cascaded Integrator Comb Filters © December 2010 Altera Corporation ...

Page 27

... Chapter 4: Functional Description Cascaded Integrator Comb Filters Data Storage Data storage in the integrators and differentiators can utilize either logic cells, or memory blocks. The type of data storage can be selected in the MegaWizard interface when the data storage options are enabled. The memory types are then selected automatically by the Quartus II software depending on the chosen device ...

Page 28

... CIC filters with the same configuration. These can be combined into one filter, which shares the adders that exist in each stage and reduces the overall resource utilization. CIC MegaCore Function User Guide Chapter 4: Functional Description Cascaded Integrator Comb Filters and lower limit is –2 . ...

Page 29

... Figure 4–6 shows an example of the MISO architecture for a CIC filter that processes a total of four channels. In this example, the symbols are multiplexed into one output Figure 4–6. Multiple Input Single Output Architecture ...

Page 30

... Figure 4–7 shows an example of the SIMO architecture for a CIC filter that processes a total of eight channels. In this example, the symbols are demultiplexed into four outputs and D, H. Figure 4–7. Single Input Multiple Output Architecture (A,B,C,D,E,F,G,H) D ...

Page 31

... The filter mode (interpolation or decimation) cannot be changed at run time. Figure 4–8 illustrates the input and output timing relationships for a variable rate change decimation CIC filter. Note how the out_valid signal changes its period according to the variable rate change. Figure 4–8. Variable Rate Change Decimation CIC Filter Timing Diagram ...

Page 32

... A MATLAB script <variation_name>_fir_comp_coeff.m is generated in the project directory by the CIC MegaCore function. You can run this script in MATLAB to generate FIR coefficients that provide appropriate passband equalization. The generated coefficients are saved in a text file, which is ready for use by the Altera FIR Compiler MegaCore function ...

Page 33

... The Avalon-ST interface can also support more complex protocols for burst and packet transfers with packets interleaved across multiple channels. The Avalon-ST interface inherently synchronizes multi-channel designs, which allows you to achieve efficient, time-multiplexed implementations without having to implement complex control logic. The Avalon-ST interface supports backpressure, which is a flow control mechanism where a sink can signal to a source to stop sending data ...

Page 34

... Any signal type not explicitly listed in the table is not used by the CIC MegaCore function f For a full description of the Avalon-ST interface protocol, refer to the Specifications. CIC MegaCore Function User Guide Table 4–1 lists the values of these parameters that are 0 ...

Page 35

... Figure 4–12 shows an example where four symbols are transferred on each beat. This multiple symbols per beat scenario applies to both the sink interface on MISO CIC filters and the source interface of SIMO CIC filters. All other interfaces operate with a single symbol per beat, but the interfaces also support multiple channels using packets. Figure 4– ...

Page 36

... If the MegaCore function is not reset, the CIC filter may produce unexpected results due to feedback signals. Optional top-level clock enable. Sample input. For multiple input cases, the input data ports are named as in0_data, in1_data, and so on. Marks the end of the incoming sample group. If there are N channels, the end of packet signal must be high when the sample belonging to the last channel, that is channel N-1, is presented at in_data ...

Page 37

... Interpolation, IEEE Transactions on Acoustics, Speech and Signal Processing, Vol. ASSP-29, pp. 155-162, April 1981. ■ U. Meyer-Baese, Digital Signal Processing with Field Programmable Gate Arrays, 2nd Edition, Spinger, 2004. ■ MegaCore IP Library Release Notes and Altera Software Installation and Licensing ■ ■ AN320: OpenCore Plus Evaluation of ■ ...

Page 38

... CIC MegaCore Function User Guide Chapter 4: Functional Description Referenced Documents © December 2010 Altera Corporation ...

Page 39

... October 2007 7.2 Full support for Arria GX ■ May 2007 7.1 Added description of new features for variable interpolation/decimation rate and ■ compensation filter coefficients generation Preliminary support for Arria™ GX ■ Full support for Stratix II GX and HardCopy ■ December 2006 7 ...

Page 40

... Active-low signals are denoted by suffix n. Example: resetn. . Indicates command line commands and anything that must be typed exactly as it appears. For example, c:\qdesigns\tutorial\chiptrip.gdf. Also indicates sections of an actual file, such as a Report File, references to parts of files (for example, the AHDL keyword SUBDESIGN), and logic function names (for example, TRI) ...

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