IP-10GETHERNET Altera, IP-10GETHERNET Datasheet
IP-10GETHERNET
Specifications of IP-10GETHERNET
Related parts for IP-10GETHERNET
IP-10GETHERNET Summary of contents
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... Innovation Drive San Jose, CA 95134 www.altera.com 10-Gbps Ethernet Reference Design User Guide IP Core Version: 10.0 Document Date: July 2010 ...
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... July 2010 Altera Corporation UG-01076-2.0 i–2 10-Gbps Ethernet Reference Design User Guide ...
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... Avalon standard XGMII interface on the network side. The XAUI interface is implemented as hard Altera FPGA transceiver or as soft logic, which results in a soft 10GBASE-X XAUI PCS. Alternatively, you can choose to implement a 10-Gbps Ethernet IP core that includes only the MAC or the soft XAUI PCS. ...
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... Programmable filtering of received frames with CRC errors, length-check error, or oversized errors. ■ Easy-to-use MegaWizard ■ IP functional simulation models for use in Altera-supported VHDL and Verilog HDL simulators. Verilog HDL and VHDL testbench and verification environment. ■ ■ Deficit Idle Count (DIC) is supported 1.2. Performance and Resource Utilization Table 1– ...
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... Yes Yes 1.3. Revision History Table 1–4 summarizes the new feature and device support history for this IP core. Table 1–4. New Features and Device Support History (Part Release 10.0 July 2010 Added support for pause frame control (PFC). Frames can ■ ...
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... Preliminary support means the IP core meets all functional requirements, but may still be undergoing timing analysis for the device family; it can be used in production designs with caution. (2) Full support means the IP core meets all functional and timing requirements for the device family and can be used in production designs. ...
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... Quartus f Refer to the Quartus II Development Software Literature the Quartus II design flow, including tutorials. 1 Altera categorizes this IP core as a reference design, described on the Altera website on the 10-Gbps Ethernet Reference Design This document describes the following development flow steps: 1. Licensing and Installation a ...
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... Depending on the phase of your design, the following licensing options are available. 2.1.1. Free Time-Limited Evaluation Using OpenCore Plus Licensing You can use the OpenCore Plus feature to temporarily try out the IP core for free using one of Altera’s development boards that include an Altera FPGA. There are two modes of operation: ■ ...
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... Plug-In Manager allows you to customize and create RTL for the IP core and then integrate this variant into your overall design. SOPC Builder allows you can add the 10-Gbps Ethernet IP core directly to a new or existing SOPC Builder system. Use this design flow if your design includes other SOPC Builder components ...
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... Under Category, click IP Search Path. 6. Click Add the Open dialog box, navigate to <ip_lib>/eth_10g/lib/ip_toolbench. 8. Click Open. 9. Click Finish. You can locate the 10G-Gbps Ethernet IP core in SOPC Builder by expanding: Interface Protocols -> Ethernet. f For more information about SOPC Builder, refer to the Quartus II Handbook. ...
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... Avalon-ST interface on the client side and standard XAUI interface on the network side. Creates a IP core that has the same functionality and external interfaces as a MAC with 10GBASE-X hard macro PHY; however, the physical coding sublayer (PCS) is implemented in soft logic instead of a hard macro.This option is only available for Stratix IV devices. 2– ...
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... Parameter Settings Soft XAUI only Soft XAUI Tx PLL Type MAC only 2.2.2. FIFO Options In most applications, the client side interface of the IP core includes a FIFO between the client and the MAC. include the FIFO in the IP core. Table 2–2. FIFO Options Parameter Value ...
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... For Arria GX devices, this option is not available. In any configuration that requires the ALTGX_RECONFIG megafunction, you must instantiate it in your design and connect it to the 10-Gbps Ethernet IP core as shown in Figure 2–3. © July 2010 Altera Corporation Description When you turn this option On, the IP core instantiates an management data I/O (MDIO) master ...
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... If you turn on the ECC Protected RAMs, the IP core includes a set of error insertion registers to support ECC testing, and a set of ECC statistics counters that accumulate the counts of various types of ECC errors as they are detected, corrected, or both detected and corrected ...
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... Their usage is explained in the following sections. 2.3.2. SOPC Builder Design Flow In SOPC Builder you add the IP core directly to a new or existing SOPC Builder system. If your system includes other SOPC Builder components, such as the Nios II processor, external memory controllers, or scatter-gather DMA controllers, you can quickly create an SOPC Builder system with an Ethernet interface ...
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... Parameterization” on page 2.3.2.2. Complete the SOPC Builder System After you define the IP core parameters, you can integrate the core into a system design and connect the 10-Gbps interfaces. This document describes a very simple SOPC Builder system that includes two additional components, the SPI Slave to Avalon-MM Master Bridge and Data Format Adapter ...
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... Chapter 2: Getting Started with the 10-Gbps Ethernet IP Design Flows Table 2–4. Avalon-ST Data Format Adapter Parameters (Part Error Signal Width (bits) Ready Latency Data Bits Per Symbol 4. Click Finish to add this component to your system complete this design, create the following connections: 6 ...
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... Altera provides a simple test infrastructure for basic functional verification of the customized IP core. This testbench is automatically generated when you generate your 10-Gbps Ethernet IP core. The details of the verification environment and how to use it is being described below. The testbench consists of the following components: ■ ...
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... This file includes tests that configure the testbench and transmit and receive packets via the MAC Tx and Rx ports. demo_run_modelsim.tcl This is the simulation script that you can use to compile all files and run the test case. 2.4.2. Testbench Utilities—Tasks and Procedures The tb_utils.v file contains many tasks and functions to configure the components of the testbench ...
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... Creates a valid frame for transfer using the Avalon-ST protocol. Getting Started with the 10-Gbps Ethernet IP Chapter 2: Getting Started with the 10-Gbps Ethernet IP The address of the register to read. The data to read from the specified address. Set the MDIO is for clause 45; set the MDIO is for clause 22. ...
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... Arguments pkt_length pkt_type min_ipg 2.4.3. Running Tests You can use the tb.v as sample test to perform preliminary verification of the IP core. You can extend this example to create other tests to create a complete verification suite. © July 2010 Altera Corporation The length of the payload in bytes. ...
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... Start transmission and clear the Rx and Tx FIFOs. 2.4.3.2. Running sample test case Before you can run the example tests, you must compile several RTL files and libraries. A script in the /tb directory performs these tasks. To run the script, complete the following tasks: 1. Change to the <project_dir>/tge_91/tb/verilog directory. ...
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... When you generate a custom 10-Gbps Ethernet IP core, the Quartus II software also generates files for timing constraints and place and route. When you instantiate your Ethernet IP core in a complete system design, you can use these scripts as a guide when creating the timing constraints for your complete system. ...
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... Client domain Interface 2.5.2. Reset Synchronization The IP core provides a separate reset pin for each clock domain. The design uses the following reset and clock pairs: reset_n—resets the sysclk clock domain. sysclk connects to the MAC Tx and ■ Rx and the MAC side of FIFO interfaces. ...
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... July 2010 Altera Corporation shows the constraints included in the .sdc for the 10-Gbps Ethernet IP for more information about clocking. Example 2–3 shows typical pin type and placement assignments. Device Handbook, Pin-Out Files for Altera web pages for the targeted Altera device to Table 2– ...
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... Getting Started with the 10-Gbps Ethernet IP Chapter 2: Getting Started with the 10-Gbps Ethernet IP Implementation and Timing Analysis © July 2010 Altera Corporation ...
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... Ethernet PHY ■ Clocks and Reset 1 Altera categorizes this IP core as a reference design, described on the Altera website on the 10-Gbps Ethernet Reference Design 3.1. Typical 10-Gbps Ethernet Systems This section provides top-level block diagrams of all of the variants that you can create when you to customize your 10-Gbps Ethernet IP core. Figure 3– ...
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... PHY. The PHY encodes the MAC frame as required for reliable transmission over the media to the remote end. Similarly, in the receive direction, the MAC accepts frames via a PHY, performs checks, generates statistics, strips out the preamble and SFD, and passes the rest of the frame to the client. ...
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... Ethernet frame payload of 64 bytes, and calculates the CRC over the entire MAC frame. (If padding is added also included in CRC calculation.) The Tx MAC module can also modify the source address, and insert interpacket gap (IPG) bytes when necessary. © July 2010 Altera Corporation Tx MAC ...
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... IPG bytes The following sections describe the functions that the Tx module performs. 3.2.1.1. Start, Preamble, and SFD Insertion In the Tx datapath the MAC appends a one-byte START, 6-byte preamble, and 1-byte SFD to the client frame ...
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... However, you can change the default IPG (in bytes) via the configuration register tx_ipg_length. You can configure the minimum IPG to any value between 8 bytes and 252 bytes times in the tx_ipg_length register. © July 2010 Altera Corporation ...
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... The deficit idle counter maintains an average IPG. You can configure the average IPG value in the tx_ipg_length register (0x05c). The number is a multiple of 4 with a minimum of 8 and a maximum of 252. The default (IEEE required value guarantee reliable PCS functionality, Altera recommends that you set the IPG to a minimum of 12 bytes ...
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... MAC/client interface when you include the optional FIFO. © July 2010 Altera Corporation avl_tx_dat[63:0] avl_st_tx_ena avl_st_tx_sop Tx avl_st_tx_eop Client FIFO avl_st_tx_err avl_st_tx_mty[2:0] avl_st_tx_dav Description Valid Data Bits avl_tx_dat[63:0] avl_tx_dat[63:8] avl_tx_dat[63:16] avl_tx_dat[63:24] avl_tx_dat[63:32] avl_tx_dat[63:40] avl_tx_dat[63:48] avl_tx_dat[63:56] 10-Gbps Ethernet IP Functional Description 3–7 Tx ...
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... Tx FIFO and is used to apply backpressure. Similarly the user_tx_dav signal controls the amount of client data available to the Tx MAC. The FIFO is 64 bits wide. All the threshold values are specified in bytes. 10-Gbps Ethernet IP Functional Description between the avl_st_tx_sop and avl_st_tx_eop signals. MAC Functional Description applies backpress © ...
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... If your design does not include the FIFO, the client should mimic the FIFO MAC interface. © July 2010 Altera Corporation tx_almost_full_on tx_almost_full_off Write Port Client Side avl_st_tx_dav (space available) tx_almost_empty_off tx_almost_empty_on Description and avl_st_tx_eop signals. The Tx MAC can apply backpressure 3–9 Read Port MAC Side user_tx_dav (data available) 10-Gbps Ethernet IP Functional Description ...
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... MAC or is guaranteed to send the entire packet once the MAC starts requesting data. If your variant includes the optional FIFO, the FIFO drives user_tx_dav, otherwise, the client interface drives user_tx_dav. 10-Gbps Ethernet IP Functional Description user_tx_dat[63:0] user_tx_data_valid user_tx_sop ...
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... PHY. When you parameterize the 10-Gbps Ethernet IP core to include both Altera MAC and integrated PHY, the MAC-PHY Tx interface is an SDR version of XGMII. When you configure the IP core to connect the Altera MAC to an external PHY, the standard DDR XGMII interface is generated this document, both SDR and DDR interfaces are generally referred to as XGMII interfaces ...
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... MAC RX Notes to Figure 3–11: (1) The SYS PLL is not part of the 10-Gbps Ethernet IP core. (2) The sysclk and the 90° phase shifted clock should come from the same PLL to ensure 0 ppm difference. Table 3–4 describes the signals that comprise this interface. Table 3–4. Tx XGMII Interface ...
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... The address arrives in the same order as it was received. The client side of Tx interface bus is big endian. © July 2010 Altera Corporation Arria II GX, Stratix II GX, Stratix IV GX, or HardCopy IV Device rs_tx_data[63:0] MAC Tx rs_tx_ctrl[7:0] Description Table 3–6 shows the fields packet. 3–13 Altera PHY (internal ALT2GX or ALTGX transceiver) 10-Gbps Ethernet IP Functional Description ...
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... Receive Data Path The Rx MAC receives Ethernet frames from the PHY and forwards the payload with relevant header bytes to the client after performing some MAC functions on header bytes. Some of the header bytes are optionally stripped from the frame before forwarding. Figure 3–14 ...
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... The preamble sequence is Start, six preamble bytes, and SFD. If this sequence is incorrect the frame is ignored. The start word must be on receive lane 0 (most significant byte). The IP core uses the SFD byte (0xD5) to identify the last byte of the preamble. The MAC Rx looks for the Start, six preamble bytes and SFD. The MAC Rx removes all Start, SFD and IFG bytes from accepted frames ...
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... The error detection capability of CRC32 code degrades if the Ethernet frame length exceeds 11,455 bytes. For more information refer to the Extended Frame Sizes for Next Generation Ethernets white paper available on the website. 10-Gbps Ethernet IP Functional Description MAC Functional Description ± 100 ppm, as defined in the IEEE Pittsburgh Supercomputing Center © ...
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... Destination Address 6 bytes Source Address 6 bytes Length/Type (VLAN Tag 0x8100) 2 bytes 2 bytes Frame Length Client Length/Type 2 bytes 0..1500/9000 bytes 0..42 bytes 4 bytes Frame Check Sequence 3–17 Start Preamble SFD VLAN Info Payload Data Pad Figure 3–15 10-Gbps Ethernet IP Functional Description ...
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... Flow Control Using Pause Frames” on page 3.2.4.11.Inter Packet Gap IPG octets received are removed by the MAC Rx and are not forwarded to the client. 3.2.4.12.Pause Ignore When this bit is set to one, the Pause frames are not processed, so that the MAC Tx traffic is not affected by the valid pause frames ...
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... Rx MAC, changing value on both edges of xgmii_rx_clk. 4-bit signal indicating when a control byte is present on corresponding xgmii_rx_data lane. xgmii_rx_data[31:0] XGMII xgmii_rx_ctrl[3:0] Module (SDR) xgmii_rx_clk 10-Gbps Ethernet IP Functional Description 3–19 ...
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... O avl_st_rx_val O avl_st_rx_sop O avl_st_rx_eop O avl_st_rx_mty[2:0] O avl_st_rx_dav I avl_st_rx_ena O avl_st_rx_vlan_tag 10-Gbps Ethernet IP Functional Description avl_st_rx_dat[63:0] avl_st_rx_val avl_st_rx_sop avl_st_rx_eop avl_st_rx_err Rx Client avl_st_rx_mty[2:0] avl_st_rx_vlan_tag avl_st_rx_vlan_vlan_tag avl_st_rx_ena avl_st_rx_dav Description 64-bit client or source data for transmission. When asserted indicates that the rest of the signals in the interface are valid. ...
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... July 2010 Altera Corporation Description Indicates the received frame is a stacked VLAN tagged frame. Marks the current client packet as errored. This signal is asserted in conjunction with avl_st_rx_eop. one cycle from ena to val Signals VLAN or stacked VLAN, if present 3–21 6 Signals error if present 10-Gbps Ethernet IP Functional Description ...
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... O user_rx_val O user_rx_sop O user_rx_eop O user_rx_mty[2:0] O user_rx_error I user_rx_vlan_tag I user_rx_vlan_vlan_tag 10-Gbps Ethernet IP Functional Description user_rx_dat[63:0] user_rx_val user_rx_sop user_rx_eop Rx FIFO user_rx_err (Sink) user_rx_mty[2:0] user_rx_vlan_tag user_rx_vlan_vlan_tag Description 64-bit client or source data for transmission. When asserted indicates that the rest of the signals in the interface are valid. Asserted for one cycle to indicate the start of a packet. ...
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... If your design includes a FIFO in store and forward mode, setting the FIFO_ERR_DIS bit the command_config register discards the errored packets in the FIFO. 3.3. ECC Options The 10-Gbps Ethernet IP core ECC feature implements single-bit error correction and double-bit error detection (SECDED). f The ALTECC megafunction performs the ECC encoding and decoding for this IP core ...
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... The Soft XAUI PCS does not report packets dropped, but a packet start or end in a XAUI FIFO can be corrupted multiple-bit error is detected, the IP core inserts a disparity error in the FIFO entry, which affects two columns. The IDLE conversion state machine translates the disparity error to a local fault error occurs during a frame, the MAC terminates the frame and asserts the ecc_mbe signal ...
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... If you use this mode be sure to size the FIFO to meet the IEEE 802.3 latency requirements. © July 2010 Altera Corporation Figure 3–22 (Note 1) DESTINATION ADDRESS[47:0] = 0x010000C28001 (2) PAUSE QUANTA[15:0] = 0x00000000 3–25 illustrates these frames. XON Frame START[7:0] PREAMBLE[47:0] SFD[7:0] SOURCE ADDR[47:0] TYPE[15:0] 0x0808 OPCODE[15:0] - 0X0001 PAD[355:0] CRC[31:0] 10-Gbps Ethernet IP Functional Description ...
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... Interface Configuration XOFF_request (client) XON_request (client) Avalon-ST FIFO Tx FIFO Tx Interface (optional) Avalon-ST FIFO Rx FIFO Rx Interface (optional) 10-Gbps Ethernet IP Functional Description XOFF_Gen XON_Gen Registers No_Pause_FIFO Client MAC Tx Tx MAC Interface Mac Data and Control Frame Generator Rx FIFO Full Indication Client MAC Rx Interface ...
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... IEEE 802.3 standard. The following functions are available in the regular mode: © July 2010 Altera Corporation MAC Client Interface MAC 3–27 Figure 3–24 illustrates the RF/IDLE rx_link_fault Network 2’b01/2’b10 Interface LF/RF 10-Gbps Ethernet IP Functional Description ...
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... Address checking ■ 3.4.4.2. Promiscuous Mode In promiscuous mode, most of the MAC functions, especially on the Rx datapath are ignored; the data is passed on to the client after stripping the preamble and SFD. The following functions are available in promiscuous mode: ■ Tx Operations Add preamble and SFD ■ ...
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... Ethernet traffic received from remote device is looped back the XGMII interface. To use this mode, complete the following steps: 1. Stop transmitting data. 2. Put the IP core into line loopback mode by completing the following steps: a. Disable the MAC Tx in the configuration register. b. Turn on line loopback mode. ...
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... Signal avalon_clk avalon_reset_n avalon_address[8:0] avalon_write avalon_writedata[31:0] avalon_waitrequest avalon_read avalon_readdata[31:0] 10-Gbps Ethernet IP Functional Description Direction I Clock input. I Active low reset bit register word address. The word address is formed by right-shifting the lower two bits of the byte address provided by an 8-bit host. For example, a byte address of 0x5C becomes a word address of 0x17 ...
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... Register Descriptions Figure 3–26 illustrates the timing for reads on the Avalon-MM interface. Figure 3–26. Typical Avalon-MM Interface TIming for Multiple Reads avalon_st_clk avalon_reset_n avalon_address[9:0] 000 avalon_write avalon_writedata[31:0] avalon_read avalon_readdata[31:0] avalon_waitrequest Figure 3–27 illustrates the timing for writes on the Avalon-MM interface. Figure 3–27. Typical Avalon-MM Interface TIming for Multiple Writes ...
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... Ethernet IP Functional Description 3–43. Description Revision. This register is divided into two 16-bit fields: Bits 15:0: IP core revision, set to ■ 0x0702 Bit 31:16: Customer specific ■ revision, set to 0 during IP core configuration. This field is controlled by the parameter CUST_VERSION defined in the top level generated for the 10-Gbps Ethernet IP core instance ...
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... Transmit FIFO almost-full threshold. The number writeable bits depends on the FIFO size. The bottom 3 bits are ignored so that a threshold of 0x100 and 0x102 is the same. 3–33 Access HW Reset SW Reset RW 1518 — — — — — — — — — — 10-Gbps Ethernet IP Functional Description ...
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... Minimum IPG. Valid values are 8–252 bytes. If this register is set to an invalid value, it defaults to 12 byte-times which is a typical value of minimum IPG. Bits 5–31 are reserved and set to read-only value 0. This register is wired to mac_0 and mac_1 addresses respectively. Table 3–18 on page 3– ...
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... Bit[0] =1'b1 and indicates a local ■ fault has been detected Bit[1] = 1'b1 and indicates a ■ remote fault has been detected Bit [1:0] = 2'b00 and indicates link ■ All other bits are currently unused. 3–35 Access HW Reset SW Reset — — 10-Gbps Ethernet IP Functional Description ...
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... Ethernet IP Functional Description Description Registers 0–31 within PHY device 0 connected to the MDIO PHY management interface. Reading or writing immediately causes the corresponding MDIO transaction to read or write the underlying PHY device register. The register at address offset 0x200 corresponds to register 0 of PHY device 0 ...
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... For more information, refer to the “Stratix IV Transceiver Architecture” chapter in the Stratix IV Device Handbook. 3–37 Access HW Reset SW Reset RW 0 — — — RW — — — — — RO — — 10-Gbps Ethernet IP Functional Description ...
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... If this bit is set to 1, the IP core forwards the CRC field to the user ■ application. If this bit is set to 0, the IP core removes the CRC field from the frame ■ before forwarding the frame to the user application. This bit is ignored if the PAD_EN bit this case, the IP core checks ■ ...
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... RW FIFO_ERR_DISC © July 2010 Altera Corporation Description Receive pause frame forwarding. Terminates or forwards pause frames. If this bit is set to 1, the IP core forwards pause frames to the user ■ application. If this bit is set to 0, the IP core terminates and discards pause frames. ■ Ignore pause frame quanta. ...
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... WC CNT_RESET 3.6.2. Software Reset A software application can reset the IP core by setting the SW_RESET bit in the command_config register to 1. During a software reset, the IP core clears all statistics registers, flushes both the Tx and Rx FIFOs, and disables the transmitter and receiver by setting the TX_ENA and RX_ENA bits in the command_config register to 0. ...
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... Frame received with an alignment error. Sum of payload and padding octets of frames transmitted without error. Sum of payload and padding octets of frames received without error. Number of transmitted pause frames. Number of received pause frames. IEEE 802.3 Standard Clause Description 10-Gbps Ethernet IP Functional Description 3–41 ...
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... MIB Object Name etherStatsDropEvents etherStatsOctets etherStatsPkts etherStatsUndersizePkts etherStatsOversizePkts etherStatsPkts64Octets etherStatsPkts65to127Octets etherStatsPkts128to255Octets etherStatsPkts256to511Octets 10-Gbps Ethernet IP Functional Description Number of frames received with one of the following errors: FIFO overflow error ■ CRC error ■ Length error ■ Terminated frame with an error or error during a frame ■ ...
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... FIFO. Support Any valid frame with Broadcast address: = ifInBroadcastPkts Any valid multicast frame, including pause frames: = ifInMulticastPkts + aPAUSEMACCtrlFramesReceived Incremented when frames of correct length but with CRC error are received: = aFrameCheckSequenceErrors 3–43 Support 10-Gbps Ethernet IP Functional Description ...
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... MAC is instantiated, they are not available in Soft XAUI only mode. However, in Soft XAUI only mode, special input signals allow software to specify Soft XAUI error injection to the IP core. Therefore, in this case you can test the ECC feature, even though the IP core does not maintain ECC testing registers or cumulative statistics information ...
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... Fatal XAUI ECC Errors Total Recovered (corrected) ECC Errors Total Fatal (detected but uncorrectable) ECC Errors Tx FIFO ECC Packets Dropped Rx FIFO ECC Packets Dropped Function Function Function 3–45 Expanded Name HW Reset Value 0x0 Reset Value 0x0 HW Reset Value 0x0 10-Gbps Ethernet IP Functional Description ...
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... Bits Access [31:13] RW Reserved. [12:0] Errors inserted in the 13-bit Rx FIFO control+ECC. For each bit position, the value 1 indicates an error is inserted, and the value 0 indicates no error is inserted. 10-Gbps Ethernet IP Functional Description Function Function Function Function Function Function © July 2010 Altera Corporation ...
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... Errors inserted in bits [27:0] of the deskew lane 3 data+ECC. For each bit position, the value 1 indicates an error is inserted, and the value 0 indicates no error is inserted. © July 2010 Altera Corporation Function Function Function Function Function 10-Gbps Ethernet IP Functional Description 3–47 HW Reset Value 0x0 ...
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... Bits Access [31:8] Reserved RC [7:0] Number of multiple-bit errors detected in Tx FIFO. These errors are not corrected. This register saturates at the value 255; after it reaches 255, it maintains this value until read. Reading this register resets it automatically. 10-Gbps Ethernet IP Functional Description Function Function ...
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... Reserved RC [7:0] Number of multiple-bit errors detected in Rx FIFO. These errors are not corrected. This register saturates at the value 255; after it reaches 255, it maintains this value until read. Reading this register resets it automatically. Table 3–46. ECC_COUNT_XAUI_SBE—Recovered XAUI ECC Errors—Offset: 0x410 ...
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... Tx FIFOs than for the Soft XAUI PCS FIFOs. In the case of the Rx and Tx FIFOs, if you enable insertion during an idle cycle, the IP core inserts the error on the first cycle of the next packet written to the FIFO. In the case of the Soft XAUI PCS FIFOs, because data is written to the FIFOs continuously, the IP core inserts errors when requested ...
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... Register Descriptions The Soft XAUI PCS rate-matching FIFO might skip a write during rate compensation. In that case, a bit error is inserted in the following write. A bit error inserted during an idle cycle might cause the MAC to ignore the next packet or insert an error in the previous packet. The Soft XAUI PCS cannot signal a dropped packet using the ecc_packet_dropped signal ...
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... Write 1 ... Table 3–53 describes the fields of the MDIO frame (Clause 22). Table 3–53. MDIO Frame Field Descriptions—Clause 22 Name Preamble. 32 bits of logical 1 sent prior to every transaction. PRE Start indication. Standard MDIO (Clause 22): 0b01. ST The opcode defines whether a read or write operation is performed: OP 0b10: a read operation is performed. ■ ...
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... The host processor can access the MDIO registers of a PHY device via an Avalon-MM interface which are mapped in the address space. Each PHY device has 32 registers. The IP core supports both Clause 22 and Clause 45, but electrical restrictions require you to choose a single clause for your design. ...
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... MDIO tristate bus. Figure 3–29. MDIO Buffer Connection 3.7. 10-Gbps Ethernet PHY This section provides a high-level description of various PHY options. 3.7.1. 10GBASE-X PHY You can use the 10GBASE-X PHY to connect a 10-Gbps Ethernet MAC to the physical media over a four-lane XAUI electrical interface running at 3 ...
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... I 3-bit configuration input for the PMA. The width depends on the device and also whether a soft or hard XAUI PCS has been selected. PMA XAUI Tx Bit Serializer pll_inclk (1) Tx PLL Rx PLL XAUI Rx CDR & De- serializer “MAC 10-Gbps Ethernet IP Functional Description 3–55 ...
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... PHY Loopback The 10-Gbps Ethernet IP core does not provide a loopback at the PMA interface. If this feature is critical to your design, you can create a MAC only option and hard XAUI block separately. The soft XAUI block does not support loopback at the PMA interface ...
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... Clocks and Reset 3.8. Clocks and Reset The clocking depends upon the variant you specify. The IP core includes at least three clock domains. A fourth clock domain controls the ALTGX_RECONFIG megafunction. The following sections illustrate the clock domains for the different configurations. 3.8.1. MAC, PHY Resets and Clocks ...
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... Figure 3–32. MAC Only Clocks Altera FPGA avl_st_tx_clk Avalon- Avalon- sysclk avalon addr & data avalon_clk Avalon-ST clock domain (avl_st_tx_clk or avl_st_rx_clk) Avalon-MM clock domain (avalon_clk) Sysclk domain (sysclk) 10-Gbps Ethernet IP Functional Description Figure 3–32 are the same as in for clarity. FIFO FIFO MAC FIFO FIFO ...
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... MHz system clock for the state machines and datapath. Can be shared with other 10 Gbps sysclk Ethernet IP cores in the same device. You must provide this clock. The sysclk phase-shifted by 90 degrees. This clock ensures that the transmitter clock and the sysclk_90 Tx data are 90 degrees apart in an XGMII interface ...
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... Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services Description “Top-Level Transceiver Signals” ...