IP-10GETHERNET Altera, IP-10GETHERNET Datasheet - Page 46

• Manufacturer Part Number: IP-10GETHERNET
• Description: IP CORE - 10 Gbps Ethernet MAC PCS PMA Reference Design
• Manufacturer: Altera

Specifications of IP-10GETHERNET

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

3–20
Table 3–9. Client Rx FIFO Interface (Part 1 of 2)
10-Gbps Ethernet IP Functional Description
avl_st_rx_dat[63:0]
avl_st_rx_val
avl_st_rx_sop
avl_st_rx_eop
avl_st_rx_mty[2:0]
avl_st_rx_dav
avl_st_rx_ena
avl_st_rx_vlan_tag
Signal Name
3.2.4.17.Client FIFO Interface
In this configuration, the Rx MAC module is connected to the client through the FIFO.
Figure 3–18
Figure 3–18. Client FIFO Interface Diagram
Table 3–9
describes the signals that comprise the standard DDR XGMII Rx interface.
Dir
O
O
O
O
O
O
O
I
illustrates the signals that comprise this interface.
64-bit client or source data for transmission.
When asserted indicates that the rest of the signals in the interface are valid.
Asserted for one cycle to indicate the start of a MAC packet.
Asserted for one cycle to indicate the end of a MAC packet.
Specifies how many bytes of avl_st_rx_dat[63:0] are empty when
avl_st_rx_eop is asserted as follows:
Value
0
1
2
3
4
5
6
7
Indicates that the FIFO has data for client’s consumption.
Read signal from the client indicating that it is ready to accept data from the FIFO.
Indicates the received frame is a VLAN tagged frame.
Client
Rx
Valid Data Bits
avl_st_rx_dat[63:0]
avl_st_rx_dat[63:8]
avl_st_rx_dat[63:16]
avl_st_rx_dat[63:24]
avl_st_rx_dat[63:32]
avl_st_rx_dat[63:40]
avl_st_rx_dat[63:48]
avl_st_rx_dat[63:56]
avl_st_rx_vlan_vlan_tag
avl_st_rx_dat[63:0]
avl_st_rx_val
avl_st_rx_sop
avl_st_rx_eop
avl_st_rx_err
avl_st_rx_mty[2:0]
avl_st_rx_vlan_tag
avl_st_rx_ena
avl_st_rx_dav
Description
FIFO
Rx
© July 2010 Altera Corporation
MAC Functional Description