IP-10GETHERNET Altera, IP-10GETHERNET Datasheet - Page 34

IP CORE - 10 Gbps Ethernet MAC PCS PMA Reference Design

IP-10GETHERNET

Manufacturer Part Number
IP-10GETHERNET
Description
IP CORE - 10 Gbps Ethernet MAC PCS PMA Reference Design
Manufacturer
Altera
Datasheet

Specifications of IP-10GETHERNET

Software Application
IP CORE, Interface And Protocols, ETHERNET
Supported Families
Quartus II
Core Architecture
FPGA
Core Sub-architecture
Stratix
Rohs Compliant
NA
Lead Free Status / RoHS Status
na
3–8
Figure 3–7. MAC/Client Interface with Tx FIFO
10-Gbps Ethernet IP Functional Description
avl_st_tx_data[63:0]
avl_st_tx_mty[2:0]
avl_st_tx_error
avl_st_reset_n
avl_st_tx_ena
avl_st_tx_eop
avl_st_tx_dav
avl_st_tx_sop
avl_st_clk
1
3.2.2.3. Tx FIFO Modes
The Tx FIFO can be configured to operate in the following two modes:
Note that when the design includes the Tx FIFO as a buffer, the client may assert
avl_st_tx_ena
However, the Tx FIFO must provide a continuous data stream to the Tx MAC.
3.2.2.4. Tx FIFO Back Pressure and Configurable Thresholds
The Tx FIFO provides four registers to dynamically configurable thresholds to
effectively manage potential overflow and underflow conditions and increase
datapath efficiency. The Tx FIFO ready signal, avl_st_tx_dav, controls the amount
of client data written to the Tx FIFO and is used to apply backpressure. Similarly the
user_tx_dav signal controls the amount of client data available to the Tx MAC. The
FIFO is 64 bits wide. All the threshold values are specified in bytes.
Store and forward—In this mode, the entire client frame is stored before it is made
available to the MAC Tx module. In the store and forward mode, you should
specify a FIFO size that can hold the longest possible frame in the system. Altera
recommends twice the maximum possible frame size.
Fill level—In the fill level mode, the data is available for the Tx MAC when a
threshold is reached or an end of packet is signal is asserted within the specified
threshold. The data is must be passed continuously from the write side to the read
side.
signals FIFO has space for data
between the avl_st_tx_sop and avl_st_tx_eop signals.
© July 2010 Altera Corporation
MAC Functional Description
applies backpress

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