IPR-10GETHERNET Altera, IPR-10GETHERNET Datasheet - Page 16

• Manufacturer Part Number: IPR-10GETHERNET
• Description: IP CORE Renewal Of IP-10GETHERNET
• Manufacturer: Altera

Specifications of IPR-10GETHERNET

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Quartus II
• Features: IEEE 802.3 2005 And 802.1Q Ethernet Standards, Management Data I/O (MDIO) Master Interface
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

2–10
Getting Started with the 10-Gbps Ethernet IP
f
1
1. Open your Quartus II project file.
2. Launch SOPC Builder from the Tools menu.
3. For a new system, specify the system name and language. This example uses the
4. Add 10-Gbps Ethernet to your system from the System Contents tab.
You can find 10-Gbps Ethernet by expanding Interface Protocols > Ethernet or by
typing any string from the component name into the search field under the
Component Library list.
5. Specify options on the Parameter Settings tab.
2.3.2.2. Complete the SOPC Builder System
After you define the IP core parameters, you can integrate the core into a system
design and connect the 10-Gbps interfaces. This document describes a very simple
SOPC Builder system that includes two additional components, the SPI Slave to
Avalon-MM Master Bridge and Data Format Adapter. The design creates a local
loopback from the Tx to the Rx interfaces of the 10-Gbps Ethernet IP core. This
example only demonstrates the SOPC Builder design flow; it is not a functional
design.
Refer to Application Note 588,
Design
Follow the steps below to complete the SOPC Builder system.
1. To add the SPI Slave to your system, expand Bridges and Adapters > Memory
2. To add the Avalon-ST Data Format Adapter to your system, expand Bridges and
3. On the Parameter Settings page, specify the following parameters shown in
Table 2–4. Avalon-ST Data Format Adapter Parameters (Part 1 of 2)
Data Symbols Per Beat
Include Empty Signal
Channel Signal Width (bits)
Max Channel
Include Packet Support
system name tge_system and selects Verilog as the Target HDL.
f
Mapped and double-click SPI Slave to Avalon Master Bridge. Click Finish to add
this component to your system.
1
Adapters > Streaming and double-click Avalon-ST Data Format Adapter.
Table
for a more complete design example.
2–4.
As you add components to your system SOPC Builder reports errors in the
console window. These errors disappear as you complete your system.
For a detailed explanation of the parameters, refer to the
Parameterization” on page
Parameter
10-Gbps Ethernet Hardware Demonstration Reference
2–4.
Chapter 2: Getting Started with the 10-Gbps Ethernet IP
8
AUTO
0
0
Turn this option on
Value
© July 2010 Altera Corporation
“IP Core
Design Flows