IPR-10GETHERNET Altera, IPR-10GETHERNET Datasheet - Page 52

• Manufacturer Part Number: IPR-10GETHERNET
• Description: IP CORE Renewal Of IP-10GETHERNET
• Manufacturer: Altera

Specifications of IPR-10GETHERNET

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Quartus II
• Features: IEEE 802.3 2005 And 802.1Q Ethernet Standards, Management Data I/O (MDIO) Master Interface
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

3–26
3.4.2. Conditions Triggering XON frame transmission
Figure 3–23. Block Diagram of Pause Transmission Logic
10-Gbps Ethernet IP Functional Description
Avalon-ST FIFO
XOFF_request (client)
XON_request (client)
Tx Interface
Avalon-ST FIFO
Avalon-MM Host
Rx Interface
Interface
■
■
The Tx MAC transmits XON frames when one of the following conditions occurs:
■
■
■
Figure 3–23
Client requests XOFF transmission—A client can explicitly request that XOFF
frames be sent using the xoff_request. When this signal is asserted for one
clock cycle, an XOFF frame is sent to the Ethernet network when the current frame
transmission completes.
Host (software) requests XOFF transmission—Setting the XOFF_GEN bit in the
command_config register triggers a request that an XOFF frame be sent.
Local device congestion clears (FIFO not full)—When the local Rx FIFO deasserts
the rx_almost_full flag, XON pause frames are sent to the remote device,
indicating congestion has ended. Setting the NO_PAUSE_FIFO bit of the
command_config register disables this behavior.
Client requests XON transmission—A client can explicitly request that XON
frames be sent using the xon_request. When this signal is asserted for one clock
cycle, an XON frame is sent to the Ethernet network.
Host (software) requests XON transmission—Setting the XON_GEN bit in the
command_config register triggers a request that an XON frame be sent.
Rx FIFO
Tx FIFO
(optional)
(optional)
provides a block diagram of the pause transmission logic.
Configuration
Rx FIFO Full Indication
Registers
Client MAC Rx
Client MAC Tx
Interface
Interface
Mac Data and Control
XOFF_Gen
XON_Gen
No_Pause_FIFO
Frame Processor
Frame Generator
Rx MAC
Tx MAC
Congestion and Flow Control Using Pause Frames
© July 2010 Altera Corporation
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