IPR-ED8B10B Altera, IPR-ED8B10B Datasheet
IPR-ED8B10B
Specifications of IPR-ED8B10B
Related parts for IPR-ED8B10B
IPR-ED8B10B Summary of contents
Page 1
... The five-bit group and the three-bit group The coded bits are named (the order is not alphabetical). These bits are also split into two groups: the six-bit group and the four-bit group Altera Corporation A-DS-IPED8B10B-1.02 8b10b Encoder/Decoder MegaCore Function ® ...
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... In applications where encoded characters are transmitted bit-serially, the comma character (K28.5) is usually used for alignment purposes as its 10-bit code is guaranteed not to occur elsewhere in the encoded bit stream, except after K28.7 which is normally only sent during diagnostic 8b10b Conversion LSB sent first Altera Corporation ...
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... If these conditions are not met, the decoder flags an error by asserting its rderr output. B For details on running disparity rules, see the IEEE 802.3z specification, paragraph 36.2.4.4. Altera Corporation 8b10b Encoder/Decoder MegaCore Function (ED8B10B) Data Sheet lists the special K codes used by the ED8B10B. Equivalent 8-Bit Codes K28.0 8'b000_11100 K28 ...
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... Setting rdin to 1 forces the encoder to produce an encoded word with negative or neutral disparity. 4 Figure 1 on page 2 shows a block diagram of the encoder. clk reset_n kin enable idle_ins datain [7:0] rdin rdforce for an illustration of the Table 1 on page 3 for kerr dataout [9:0] valid rdout rdcascade Altera Corporation ...
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... Note: (1) The enable, idle_ins, and rdforce signals are set high (logic 1). Altera Corporation 8b10b Encoder/Decoder MegaCore Function (ED8B10B) Data Sheet Figure 3 shows two encoders connected together to kerr dataout [9:0] valid rdout rdcascade kerr ...
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... The _pre2 registers are set at the same time as datain and kin. reg rdforce_pre2; reg rdin_pre2; // The _pre1 registers provide an extra clock tick of delay reg rdforce_pre1; reg rdin_pre1; always @ (posedge clk) begin rdforce <= rdforce_pre1; rdforce_pre1 <= rdforce_pre2; rdin <= rdin_pre1; rdin_pre1 <= rdin_pre2; end 6 Figure 4 on page 7). Altera Corporation ...
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... When the idle_del signal is asserted, it deletes all 10-bit words identified as the special IDLE character of K28.5. When the receiver detects a disparity error, the rderr signal is asserted. Figure 5 Figure 5. ED8B10B Decoder Altera Corporation 8b10b Encoder/Decoder MegaCore Function (ED8B10B) Data Sheet n n+1 n+2 a ...
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... Figure 6. Decoder Timing Diagram clk datain, enable dataout, kout, kerr, rdout, rderr rdforce, rdin 8 Figure 4 on page 7). n n Altera Corporation ...
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... Input idle_del Input enable Input datain[9:0] Altera Corporation 8b10b Encoder/Decoder MegaCore Function (ED8B10B) Data Sheet and 3 list the input/output signals for the encoder, and decoder. Description Clock. The input is latched, and the result is output on this clock. There is a three clock cycle latency between the input and output. ...
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... Cascaded Running disparity. Used when decoders are cascaded. shows the required speed and estimated gate count of the Mode LEs/LCs ESBs/EABs 56 133 56 137 58 129 f (MHz) MAX (2) 2 173 0 150 (2) 1 216 0 223 (2) 2 138 0 147 Altera Corporation ...
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