IPR-PCIE/4 Altera, IPR-PCIE/4 Datasheet - Page 117
IPR-PCIE/4
Manufacturer Part Number
IPR-PCIE/4
Description
IP CORE Renewal Of IP-PCIE/4
Manufacturer
Altera
Type
MegaCorer
Specifications of IPR-PCIE/4
Software Application
IP CORE, Interface And Protocols, PCI
Supported Families
Arria GX, Cyclone II, HardCopy II, Stratix II
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Function
PCI Express Compiler, x4 Link Width
License
Renewal License
Lead Free Status / RoHS Status
na
Lead Free Status / RoHS Status
na
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Chapter 5: IP Core Interfaces
Avalon-ST Interface
December 2010 Altera Corporation
Configuration Space Register Access Timing
Figure 5–30
Cyclone IV GX, HardCopy IV, and Stratix IV GX devices when using a 64-bit
interface.
Figure 5–30. tl_cfg_ctl Timing (Hard IP Implementation)
Figure 5–31
Cyclone IV GX, HardCopy IV, and Stratix IV GX devices when using a 128-bit
interface.
Figure 5–31. tl_cfg_ctl Timing (Hard IP Implementation)
Figure 5–32
Cyclone IV GX, HardCopy IV, and Stratix IV GX devices when using a 64-bit
interface.
Figure 5–32. tl_cfg_sts Timing (Hard IP Implementation)
Figure 5–33
Cyclone IV GX, HardCopy IV, and Stratix IV GX devices when using a 128-bit
interface.
Figure 5–33. tl_cfg_sts Timing (Hard IP Implementation)
pld_clk 128-bit mode
pld_clk 128-bit mode
pld_clk 64-bit mode
pld_clk 64-bit mode
tl_cfg_sts[52:0]
tl_cfg_add[3:0]
tl_cfg_ctl[31:0]
tl_cfg_sts[52:0]
tl_cfg_add[3:0]
tl_cfg_ctl[31:0]
tl_cfg_sts_wr
tl_cfg_ctl_wr
tl_cfg_sts_wr
tl_cfg_ctl_wr
illustrates the timing of the tl_cfg_ctl interface for the Arria II GX,
illustrates the timing of the tl_cfg_ctl interface for the Arria II GX,
illustrates the timing of the tl_cfg_sts interface for the Arria II GX,
illustrates the timing of the tl_cfg_sts interface for the Arria II GX,
core_clk
core_clk
core_clk
core_clk
data0
addr0
data0
data0
addr0
data0
data1
addr1
data1
data1
addr1
data1
PCI Express Compiler User Guide
5–33
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