IPR-PCIE/4 Altera, IPR-PCIE/4 Datasheet - Page 33
IPR-PCIE/4
Manufacturer Part Number
IPR-PCIE/4
Description
IP CORE Renewal Of IP-PCIE/4
Manufacturer
Altera
Type
MegaCorer
Specifications of IPR-PCIE/4
Software Application
IP CORE, Interface And Protocols, PCI
Supported Families
Arria GX, Cyclone II, HardCopy II, Stratix II
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Function
PCI Express Compiler, x4 Link Width
License
Renewal License
Lead Free Status / RoHS Status
na
Lead Free Status / RoHS Status
na
- Current page: 33 of 362
- Download datasheet (7Mb)
Chapter 2: Getting Started
View Generated Files
0
Figure 2–4. Directory Structure for PCI Express IP Core and Testbench
Notes to
(1) The chaining_dma directory contains the Quartus II project and settings files.
(2) <variation>_plus.v is only available for the hard IP implementation.
December 2010 Altera Corporation
Figure
Simulation and
Compilation
Quartus II
2–4:
■
IP Core Files
PCI Express
The simulation files for the chaining DMA design example, stored in the
<working_dir>\top_examples\chaining_dma\testbench sub-directory. The
Quartus II software generates the testbench files if you turn on Generate
simulation model on the EDA tab while generating the PCIe IP core.
Design Example
Testbench and
Files
<working_dir>
<variation>.v = top.v, the parameterized PCI Express IP Core
<variation>.sdc = top.sdc, the timing constraints file
<variation>.tcl = top.tcl, general Quartus II settings
pci_express_compiler-library
contains local copy of the pci express library files needed for
simulation, or compilation, or both
<variation>_examples = top_examples
common
chaining_dma, files to implement the chaining DMA
<variation>
the parameterized PCI Express IP Core including reset and
calibration circuitry
(1) (2)
Includes testbench and incremental compile directories
top_example_chaining_top.qpf, the Quartus II project file
top_example_chaining_top.qsf, the Quartus II settings file
testbench, scripts to run the testbench
runtb.do, script to run the testbench
<variation>_chaining_testbench = top_chaining_testbench.v
altpcietb_bfm_driver_chaining.v , provides test stimulus
_plus
.v> = top_plus.v,
PCI Express Compiler User Guide
2–7
Related parts for IPR-PCIE/4
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
IP CORE Renewal Of IP-PCI/MT32
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP CORE Renewal Of IP-PCI/MT64
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP CORE Renewal Of IP-PCI/T32
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP CORE Renewal Of IP-PCI/T64
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP CORE Renewal Of IP-PCIE/1
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP CORE Renewal Of IP-PCIE/8
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP NIOS II MEGACORE RENEW
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP CORE Renewal Of IP-XAUIPCS
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet: