IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 166
IPR-PCIE/8
Manufacturer Part Number
IPR-PCIE/8
Description
IP CORE Renewal Of IP-PCIE/8
Manufacturer
Altera
Type
MegaCorer
Specifications of IPR-PCIE/8
Software Application
IP CORE, Interface And Protocols, PCI
Supported Families
Arria GX, Cyclone II, HardCopy II, Stratix II
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Function
PCI Express Compiler, x8 Link Width
License
Renewal License
Lead Free Status / RoHS Status
na
Lead Free Status / RoHS Status
na
- Current page: 166 of 362
- Download datasheet (7Mb)
7–6
PCI Express Compiler User Guide
■
■
■
For endpoints, whenever the l2_exit, hotrst_exit, dlup_exit, or other
power-on-reset signals are asserted, srst and crst should be asserted for one or more
cycles for the soft IP implementation and for at least two clock cycles for hard IP
implementation.
Figure 7–5
Figure 7–5. Reset Signal Domains
For root ports, srst should be asserted whenever l2_exit, hotrst_exit, dlup_exit,
and power-on-reset signals are asserted. The root port crst signal should be asserted
whenever l2_exit, hotrst_exit and other power-on-reset signals are asserted. When
the perst# signal is asserted, srst and crst should be asserted for a longer period of
time to ensure that the root complex is stable and ready for link training.
Reset Signal Domains, ×8 Soft IP Implementation
The PCI Express IP core soft IP implementation (×8) has the following two reset
inputs:
npor—The npor signal is used internally for all sticky registers that may not be
reset in L2 low power mode or by the fundamental reset). npor is typically
generated by a logical OR of the power-on-reset generator and the perst signal as
specified in the PCI Express card electromechanical specification.
srst— The srst signal initiates a synchronous reset of the datapath state
machines.
crst—The crst signal initiates a synchronous reset of the nonsticky configuration
space registers.
provides a simplified view of the logic controlled by the reset signals.
npor
crst
srst
<variant>. v or .vhd
<variant> _core.v or .vhd
altpcie_hip_pipen1b.v or .vhd
Datapath State Machines of
Non-Sticky Registers
Configuration Space
Configuration Space
MegaCore Fucntion
Sticky Registers
SERDES Reset
State Machine
December 2010 Altera Corporation
Chapter 7: Reset and Clocks
Reset in Stratix V Devices
Related parts for IPR-PCIE/8
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
IP CORE Renewal Of IP-PCI/MT32
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP CORE Renewal Of IP-PCI/MT64
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP CORE Renewal Of IP-PCI/T32
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP CORE Renewal Of IP-PCI/T64
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP CORE Renewal Of IP-PCIE/1
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP CORE Renewal Of IP-PCIE/4
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP NIOS II MEGACORE RENEW
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP CORE Renewal Of IP-XAUIPCS
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet: