SM1211E915 Semtech, SM1211E915 Datasheet - Page 44

• Manufacturer Part Number: SM1211E915
• Description: Dev Kit Accessory
• Manufacturer: Semtech

Specifications of SM1211E915

• Modulation Type: FSK, OOK
• Data Rate Max: 200Kbps
• Frequency Range: 902MHz To 928MHz
• Supply Voltage Range: 2.1V To 3.6V
• Module Interface: SPI
• Supply Current: 25mA
• Accessory Type: RF Module
• Sensitivity: -105dBm
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Package Type: TQFN EP
• Operating Supply Voltage (min): 2.1V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Sensitivity (dbm): -105dBm
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

As illustrated in Figure 38, for Buffered mode operation the NRZ data to (from) the (de)modulator is not directly
accessed by the uC but stored in the FIFO and accessed via the SPI Data interface. This frees the uC for other
tasks between processing data from the SX1211, furthermore it simplifies software development and reduces uC
performance requirements (speed, reactivity). Note that in this mode the packet handler stays inactive.
An important feature is also the ability to empty the FIFO in Stby mode, ensuring low power consumption and
adding greater software flexibility.
Note that Bit Synchronizer is automatically enabled in Buffered mode. The Sync word recognition must be enabled
(RXParam_Sync_on=1) independently of the FIFO filling method selected (IRQParam_Fifo_fill_method).
After entering Tx in Buffered mode, the chip expects the uC to write into the FIFO, via the SPI Data interface, all the
data bytes to be transmitted (preamble, Sync word, payload...).
Actual transmission of first byte will start either when the FIFO is not empty (i.e. first byte written by the uC) or when
the FIFO is full depending on bit IRQParam_Tx_start_irq_0.
In Buffered mode the packet length is not limited, i.e. as long as there are bytes inside the FIFO they are sent.
When the last byte is transferred to the SR, /Fifoempty IRQ source is asserted to warn the uC, at that time FIFO
can still be filled with additional bytes if needed.
When the last bit of the last byte has left the SR (i.e. 8 bit periods later), the Tx_done interrupt source is asserted
and the user can exit Tx mode after waiting at least 1 bit period from the last bit processed by modulator.
Rev 7 – Sept 2
ADVANCED COMMUNICATIONS & SENSING
Data
5.4. Buffered Mode
Datapath
5.4.1. General Description
5.4.2. Tx Processing
nd
Tx
Rx
, 2008
RECOG.
SYNC
Figure 38: Buffered Mode Conceptual View
SX1211
CONTROL
Page 44 of 92
(+SR)
FIFO
CONFIG
DATA
SPI
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NSS_CONFIG
SCK
MOSI
MISO
IRQ_1
NSS_DATA
SX1211
IRQ_0