PN5120A0HN/C1,557 NXP Semiconductors, PN5120A0HN/C1,557 Datasheet - Page 31
PN5120A0HN/C1,557
Manufacturer Part Number
PN5120A0HN/C1,557
Description
IC TRANSMISSION MOD 40-HVQFN
Manufacturer
NXP Semiconductors
Datasheet
1.PN5120A0HN1C2118.pdf
(125 pages)
Specifications of PN5120A0HN/C1,557
Rf Type
Read / Write
Frequency
13.56MHz
Features
ISO14443-A, ISO14443-B
Package / Case
40-VFQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PN512
Product data sheet
COMPANY PUBLIC
9.2.1.15 CollReg
Defines the first bit collision detected on the RF interface.
Table 44.
Table 45.
Bit
7
6
5
4 to 0
Access
Rights
Symbol
ValuesAfterColl
-
CollPosNotValid
CollPos
AfterColl
CollReg register (address 0Eh); reset value: XXh, 101XXXXXb
Description of CollReg bits
Values
r/w
7
All information provided in this document is subject to legal disclaimers.
RFU
Rev. 3.6 — 10 March 2011
6
0
Description
If this bit is set to logic 0, all receiving bits will be cleared after a
collision. This bit shall only be used during bitwise anticollision at
106 kbit, otherwise it shall be set to logic 1.
Reserved for future use.
Set to logic 1, if no Collision is detected or the Position of the
Collision is out of the range of bits CollPos. This bit shall only be
interpreted in Passive Communication mode at 106 kbit or
ISO/IEC 14443A/MIFARE Reader/Writer mode.
These bits show the bit position of the first detected collision in a
received frame, only data bits are interpreted.
Example:
00h
01h
08h
These bits shall only be interpreted in Passive Communication mode
at 106 kbit or ISO/IEC 14443A/MIFARE Reader/Writer mode if bit
CollPosNotValid is set to logic 0.
NotValid
111336
CollPos
indicates a bit collision in the 32
indicates a bit collision in the 1
indicates a bit collision in the 8
5
r
4
r
3
r
st
th
CollPos
th
bit
bit
bit
2
r
Transmission module
© NXP B.V. 2011. All rights reserved.
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