S1D15206F00A200 Epson, S1D15206F00A200 Datasheet - Page 102

• Manufacturer Part Number: S1D15206F00A200
• Description: LCD Drivers LCD DRIVER
• Manufacturer: Epson

Specifications of S1D15206F00A200

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

S1D15206 Series
7. COMMANDS
Page 4–21 lists available commands. The S1D15206 series uses a
combination of A0, RD and WR (or R/W) signals to identify data bus
signals. As the chip analyzes and executes each command using
internal timing clock only (any external clock is required), its
processing speed is very HIGH and its busy check is usually not
required.
(1) Display ON/OFF
(2) Initial Display Line
(3) Set Page Address
(4) Set Column Address
4–18
A0 RD WR D7
A0
A0
0
A4
A2
0
0
0
0
0
1
1
0
0
0
0
1
The display turns off when D goes low, and it turns on when D
goes HIGH.
Alternatively turns the display on and off.
Specifies line address (refer to Figure 4) to determine the initial
display line, or COM0. The RAM display data becomes the top
line of LCD screen. It is followed by the higher number of lines
in ascending order, corresponding to the duty cycle. When this
command changes the line address, the smooth scrolling or
page change takes place.
Specifies page address to load display RAM data to page
address register. Any RAM data bit can be accessed when its
page address and column address are specified. The display
remains unchanged even when the page address is changed.
Page address 4 is the display RAM area dedicate to the indica-
tor, and only D0 is valid for data change.
Specifies column address of display RAM. When the micro-
processor repeats to access to the display RAM, the column
address counter is incremented by 1 during each access until
address 80 is accessed. The page address is not changed during
this time.
RD WR D7
RD WR D7
1
1
1
A3
A1
0
0
0
1
1
0
0
1
1
0
R/W
R/W
R/W
0
0
0
A2
A0
0
0
0
1
1
0
1
0
1
0
:
1
1
1
D6
D6
D6
A1
1
0
0
0
0
1
1
1
Page Address
D5
D5
D5
0
1
1
A0
0
1
0
0
1
0
1
2
3
4
F4
A4
F4
F4
0
1
D3
A3
D3
D3
1
1
Line address
D2
A2
D2
D2
A2
1
3 0
3 1
HIGH-order bit
0
1
2
:
D1
A1
D1
D1
A1
1
D0
A0
D0
D0
A0
D
EPSON
(5) Read Status
BUSY:
ADC:
ON/OFF: Indicates whether the display is on or off. When goes low,
RESET: Indicates the initialization is in progress by SR1 and
PS:
(6) Write Display Data
(7) Read Display Data
(8) ADC Select
A6
A0
A0
A0
A0
0
0
1
0
0
1
1
Writes 8-bit data in display RAM. As the column address is
incremented by 1 automatically after each write, the microproc-
essor can continue to write data of multiple words.
Reads 8-bit data from display RAM area specified by column
address and page address. As the column address is incremented
by 1 automatically after each write, the microprocessor can
continue to read data of multiple words. A single dummy read
is required immediately after column address setup. Refer to
the display RAM section of FUNCTIONAL DESCRIPTION
for details.
Changes the relationship between RAM column address and
segment driver. The order of segment driver output pins can be
reversed by software. This allows flexible IC layout during
LCD module assembly. For details, refer to the column address
section of Figure 4. When display data is written or read, the
column address is incremented by 1 as shown in Figure 4.
RD WR D7
RD WR D7
RD WR D7
RD WR D7
A5
1
0
1
0
0
0
0
Indicates the relationship between RAM column address
When high, the S1D15206 series is busy due to internal
operation or reset. Any command is rejected until BUSY
goes LOW. The busy check is not required if enough time
is provided for each cycle.
and segment drivers. When LOW, the display is normal
and column address “79-n” corresponds to segment driver
n. When HIGH, the display is reversed and column
address n corresponds to segment driver n.
the display turns on. When goes HIGH, the display turns
off. This is the opposite of Display ON/OFF command.
SR2 to go LOW or by Reset command. When LOW,
the display is on. When HIGH, the chip is being reset.
When LOW, LCD panel is in Power Save mode.
R/W
R/W
R/W
R/W
A4
0
1
0
1
0
0
0
:
BUSY ADC ON/OFF RESET PS
0
A3
0
0
1
D6
A6
D6
D6
D6
A2
0
0
1
D5
A5
D5
D5
D5
A1
Write data
Read data
0
0
1
A4
F4
F4
F4
F4
A0
0
1
1
D3
D3
D3
D3
A3
Column address
D2
D2
D2
D2
A2
0
7 9
0
1
:
D1
A1
D1
D1
D1
0
Rev.3.5
D0
D0
D0
D0
A0
0