S1D15206F00A200 Epson, S1D15206F00A200 Datasheet - Page 65
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S1D15206F00A200
Manufacturer Part Number
S1D15206F00A200
Description
LCD Drivers LCD DRIVER
Manufacturer
Epson
Datasheet
1.S1D15206F00A200.pdf
(612 pages)
Specifications of S1D15206F00A200
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Part Number:
S1D15206F00A200
Manufacturer:
EPSON/爱普生
Quantity:
20 000
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7. FUNCTION DESCRIPTION
System Bus
(1) MPU interface
Data transfer
The S1D15210 drivers use the A0, E (or RD) and R/W (or
WR) signals to transfer data between the system MPU
and internal registers. The combinations used are given
in the table blow.
Access to Display Date Ram and Internal
Registers
In order to match the timing requirements of the MPU
with those of the display data RAM and control registers
all data is latched into and out of the driver.
This introduces a one cycle delay between a read request
for data and the data arriving. For example when the
MPU executes a read cycle to access display RAM the
Rev. 1.1
Common
Selecting an interface type
The S1D15210 series transfers data via 8-bit bidirec-
tional data buses (D0 to D7). As its Reset pin has the
MPU interface select function, the 80-series MPU or
the 68-series MPU can directly be connected to the
MPU bus by the selection of high or low RES signal
RES signal input level
A0
1
1
0
0
Active
Active
RD
0
1
0
1
80 MPU
MPU type
80-series
68-series
WR
1
0
1
0
68 MPU
A0
R/W
A0
A0
EPSON
1
0
1
0
Table 1
Table 2
current contents of the latch are placed on the system data
bus while the desired contents of the display RAM are
moved into the latch.
This means that a dummy read cycle has to be executed
at the start of every series of reads. See Figure 1.
No dummy cycle is required at the start of a series of
writes as data is transferred automatically from the input
latch to its destination.
level after reset (see Table 1).
When the CS signal is high, the S1D15210 series is
disconnected from the MPU bus and set to stand by.
(However, the reset signal is entered regardless of the
internal setup status.)
RD
RD
Read display data
Write display data
Read status
Write to internal register (command)
E
R/W
WR
WR
Function
CS
CS
CS
S1D15210 Series
D0 to D7
D0 to D7
D0 to D7
3–7
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