IR1153SPBF International Rectifier, IR1153SPBF Datasheet - Page 9

• Manufacturer Part Number: IR1153SPBF
• Description: IC PFC ONE CYCLE CONTROL 8SOIC
• Manufacturer: International Rectifier

Specifications of IR1153SPBF

• Mode: Continuous Conduction (CCM)
• Frequency - Switching: 18.3kHz ~ 25kHz
• Current - Startup: 26µA
• Voltage - Supply: 14 V ~ 17 V
• Operating Temperature: -25°C ~ 125°C
• Mounting Type: *
• Package / Case: *
• Startup Current: 26µA
• Operating Supply Current: 7mA
• Duty Cycle (%): 99%
• Frequency: 22.2kHz
• Digital Ic Case Style: SOIC
• No. Of Pins: 8
• Operating Temperature Range: -25°C To +125°C
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• Supply Voltage Range: 14V To 17V
• Package: 8-lead SOIC
• Circuit: PFC IC
• Vcc Range (v): 14V-17V
• Out Peak Current (a): +/- 0.75
• Switching Frequency (khz): 22.2
• Environment: Industrial
• Over-voltage Protection: Yes
• Brown-out Protection: Yes
• Pbf: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Programmable Soft Start
The soft start process controls the rate of rise of the
voltage feedback loop error signal thus providing a
linear increase of the RMS input current that the
PFC converter will admit. The soft start time is
essentially controlled by voltage error amplifier
compensation
therefore user programmable to some degree
based on desired voltage feedback loop crossover
frequency.
Gate Drive Capability
The gate drive output stage of the IC is a totem
pole driver with 750mA peak current drive
capability. The gate drive is internally clamped at
14.1V (Typ). Gate drive buffer circuits (especially
cost-effective base-followers) can be easily driven
with the GATE pin of the IC to suit any system
power level.
System Protection Features
IR1153 protection features include Brown-out
protection (BOP), Open-loop protection (OLP),
Overvoltage protection (OVP), Cycle-by-cycle peak
current limit (IPK LIMIT), Soft-current limit and VCC
under voltage lock-out (UVLO).
- BOP is based on direct input line sensing using a
resistor divider/RC filter network. If BOP pin falls
below the Brown-out protection threshold V
Brown-out situation is immediately detected the
following response is executed - the gate drive
pulse is disabled, VCOMP is actively discharged
and IC is pushed into Stand-by Mode. The IC re-
enters normal operation only after BOP pin
exceeds V
Stand-by Mode until this pin exceeds V
- OLP is activated whenever the VFB pin voltage
falls below V
detected the following response is immediately
executed - the gate drive is immediately disabled,
VCOMP is actively discharged and the IC is
pushed into Stand-by mode. There is no voltage
hysteresis associated with this feature. During
start-up the IC is held in Stand-by Mode until VFB
exceeds V
IR1153 General Description
OLP
BOP(EN)
.
OLP
components
. During start-up the IC is held in
threshold. Once open loop is
selected
BOP(EN)
and
.
BOP
, a
is
9
- The OVP pin is a dedicated pin for overvoltage
protection that safeguards the system even if
there is a break in the VFB feedback loop due to
resistor divider failure etc. An overvoltage fault is
triggered when OVP pin voltage exceeds the V
threshold of 106%VREF. The response of the IC
is to immediately terminate the gate drive output
and hold it in that state. The gate drive is re-
enabled only after OVP pin voltage drops below
V
voltage level at which overvoltage protection is
triggered can be programmed by the user by
carefully designing the OVP pin resistor divider. It
is recommended NOT to set the OVP voltage
trigger limit less than 106% of DC bus voltage,
since this can endanger the situation where the
OVP reset limit will be less than the DC bus
voltage regulation point – in this condition the
voltage loop can become unstable.
- Soft-current limit is an output voltage fold-back
type protection feature encountered when the
PFC converter input current exceeds to a point
where the V
earlier, the amplitude of input current is directly
proportional to V
feedback loop.
maximum voltage inside the IC (given by
V
current causes the V
maximum value, then any further increase in input
current will cause the duty cycle to droop which
immediately forces the V
converter to fold-back. Since the highest current
is at the peak of the AC sinusoid, the droop in
duty cycle commences at the peak of the AC
sinusoid
encountered. In most converters, the design of
the current sense resistor is performed based on
soft-current limit (i.e. V
system condition which demands highest input
current (minimum V
- Cycle-by-cycle peak current limit protection
instantaneously
whenever the ISNS pin voltage exceeds V
threshold in magnitude. The gate drive is held in
the low state as long as the overcurrent condition
persists. The gate drive is re-enabled when the
magnitude of ISNS pin voltage falls below the
V
incorporates a leading edge blanking circuit to
improve noise immunity.
OVP(RST)
COMP,EFF
ISNS(PK)
threshold of 103% VREF. The exact
parameter in datasheet). If the input
threshold.
when
m
voltage saturates. As mentioned
turns-off
m
V
AC
, the error voltage of the
the
m
m
& maximum P
This
is clamped to a certain
voltage to saturate at its
m
OUT
soft-current
saturation) and at the
© 2011 International Rectifier
voltage of the PFC
the
protection
IR1153S
gate
OUT
).
limit
feature
output
ISNS(PK)
OVP
is