MA160014 Microchip Technology, MA160014 Datasheet - Page 54

• Manufacturer Part Number: MA160014
• Description: MOD PLUG-IN 44PIN PIC18LF45K22
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of MA160014

• Accessory Type: Plug-In Module (PIM) - PIC18LF45K10
• Product: Microcontroller Modules
• Data Bus Width: 8 bit
• Core Processor: PIC18LF45K22
• Interface Type: I2C, SPI
• Operating Supply Voltage: 1.8 V to 5.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: PICDEM PIC18 Explorer, DM183032
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18(L)F2X/4XK22
3.5
An exit from Sleep mode or any of the Idle modes is
triggered by any one of the following:
• an interrupt
• a Reset
• a Watchdog Time-out
This section discusses the triggers that cause exits
from power-managed modes. The clocking subsystem
actions are discussed in each of the power-managed
modes (see
“Sleep Mode”
3.5.1
Any of the available interrupt sources can cause the
device to exit from an Idle mode or the Sleep mode to
a Run mode. To enable this functionality, an interrupt
source must be enabled by setting its enable bit in one
of the INTCON or PIE registers. The exit sequence is
initiated when the corresponding interrupt flag bit is set.
The instruction immediately following the SLEEP
instruction is executed on all exits by interrupt from Idle
or Sleep modes. Code execution then branches to the
interrupt vector if the GIE/GIEH bit of the INTCON
register is set, otherwise code execution continues
without branching (see Section 9.0 “Interrupts”).
A fixed delay of interval T
is required when leaving Sleep and Idle modes. This
delay is required for the CPU to prepare for execution.
Instruction execution resumes on the first clock cycle
following this delay.
DS41412D-page 54
Exiting Idle and Sleep Modes
EXIT BY INTERRUPT
Section 3.2 “Run
and
Section 3.4 “Idle
CSD
following the wake event
Modes”,
Modes”).
Section 3.3
Preliminary
3.5.2
A WDT time-out will cause different actions depending
on which power-managed mode the device is in when
the time-out occurs.
If the device is not executing code (all Idle modes and
Sleep mode), the time-out will result in an exit from the
power-managed
Modes”
is executing code (all Run modes), the time-out will
result in a WDT Reset (see
Timer
The WDT timer and postscaler are cleared by any one
of the following:
• executing a SLEEP instruction
• executing a CLRWDT instruction
• the loss of the currently selected clock source
• modifying the IRCF bits in the OSCCON register
3.5.3
Exiting Sleep and Idle modes by Reset causes code
execution to restart at address 0. See Section 4.0
“Reset” for more details.
The exit delay time from Reset to the start of code
execution depends on both the clock sources before
and after the wake-up and the type of oscillator. Exit
delays are summarized in
3.5.4
Certain exits from power-managed modes do not
invoke the OST at all. There are two cases:
• PRI_IDLE mode, where the primary clock source
• the primary clock source is not any of the LP, XT,
In these instances, the primary clock source either
does not require an oscillator start-up delay since it is
already running (PRI_IDLE), or normally does not
require an oscillator start-up delay (RC, EC, INTOSC,
and INTOSCIO modes). However, a fixed delay of
interval T
when leaving Sleep and Idle modes to allow the CPU
to prepare for execution. Instruction execution resumes
on the first clock cycle following this delay.
when the Fail-Safe Clock Monitor is enabled
when the internal oscillator block is the device
clock source
is not stopped and
HS or HSPLL modes.
(WDT)”).
and
CSD
EXIT BY WDT TIME-OUT
EXIT BY RESET
EXIT WITHOUT AN OSCILLATOR
START-UP DELAY
Section 3.3 “Sleep
following the wake event is still required
mode
 2010 Microchip Technology Inc.
Table
(see
Section 24.2 “Watchdog
3-3.
Mode”). If the device
Section 3.2
“Run