PAC-POWR607-EV Lattice, PAC-POWR607-EV Datasheet - Page 2

• Manufacturer Part Number: PAC-POWR607-EV
• Description: MCU, MPU & DSP Development Tools ispPAC POWR607 EVAL BRD
• Manufacturer: Lattice
• Series: ispPAC®r

Specifications of PAC-POWR607-EV

• Processor To Be Evaluated: ispPAC-POWR607
• Interface Type: JTAG
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3.96 V
• Core Architecture: CPLD
• Main Purpose: Power Management, Power Supply Supervisor/Tracker/Sequencer
• Embedded: Yes, Other
• Utilized Ic / Part: ispPAC-POWR607
• Primary Attributes: -
• Secondary Attributes: 4.5 ~ 9 V Supply
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ispPAC-POWR607
Lattice Semiconductor
Evaluation Board User’s Guide
Introduction
®
Lattice Semiconductor’s Power Manager II ispPAC
-POWR607 device simplifies power supply design by integrat-
ing the analog and digital functions of power supply management (sequencing, monitoring, reset generation into a
single device). This device provides designers with a rich set of features: precision comparators with a built-in volt-
age reference, MOSFET drivers and a programmable logic device (PLD) for sequencing and supervisory logic
functions or reset control. Configuration for all subsystems in the ispPAC-POWR607 device is stored in non-volatile
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®
E
CMOS
memory. Programming is performed via the industry-standard JTAG IEEE 1149.1 interface.
PAC-POWR607-EV Evaluation Board
The PAC-POWR607-EV evaluation board (Figure 1) allows the designer to quickly configure and evaluate the isp-
PAC-POWR607 device on a fully assembled printed-circuit board. The board supports a 32-pin QFN package,
pads for user I/O, a JTAG programming cable connector, LEDs and switches. JTAG programming signals can be
®
generated by using an ispDOWNLOAD
programming cable connected between the evaluation board and a PC’s
parallel (printer) port. Both analog and digital features of the ispPACPOWR607device can be easily configured
®
using PAC-Designer
software.
Figure 1. PAC-POWR607-EV Evaluation Board
Programming Interface
Lattice Semiconductor’s ispDOWNLOAD cable can be used to program the ispPAC-POWR607 device on the eval-
uation board. This cable plugs into a PC-compatible’s parallel port connector, and includes active buffer circuitry
inside its DB-25 connector housing. The other end of the ispDOWNLOAD cable terminates in an 8-pin 0.100” pitch
header connector, which plugs directly into a mating connector, (J3) provided on the PAC-POWR607-EV evaluation
board.
Important Note: The board must be un-powered when connecting, disconnecting, or reconnecting the ispDOWN-
LOAD Cable. Always connect the ispDOWNLOAD Cable's GND pin (black wire), before connecting any other JTAG
pins. Failure to follow these procedures can in result in damage to the ispPAC-POWR607 device and render the
board inoperable.
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