LFXP2-17E-L-EVN Lattice, LFXP2-17E-L-EVN Datasheet
LFXP2-17E-L-EVN
Specifications of LFXP2-17E-L-EVN
Related parts for LFXP2-17E-L-EVN
LFXP2-17E-L-EVN Summary of contents
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... LatticeXP2 Standard Evaluation Board User’s Guide February 2010 Revision: EB29_01.5 ...
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... A platform for evaluating the Input/Output (I/O) characteristics of the FPGA Features Key features of the LatticeXP2 Standard Evaluation Board include: • LatticeXP2 FPGA 484-pin fine pitch Ball Grid Array device (LFXP2-17E-6F484C) • Single printed circuit board solution • Eight LEDs for visual feedback • ...
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... The CF connector is also useful for expansion purposes. It provides the ability to add storage, or communication capabilities to the board. Other features on the board are useful for evaluation of the LatticeXP2 FPGA or development of more complex solutions. The A/D, D/A, and digital potentiometer are helpful for mixed signal applications. SMA connections can be used for the evaluation of high-speed differential signals, and protocols ...
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... The Power Manager uses this supply rail to boot and run a power up sequence. While the LatticeXP2 does not require any specific order for the voltage rails to be applied, the Power Manager can be used to try a wide variety of sequence options. ...
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... Programmability There are three programmable devices on the board. Of primary interest for the FPGA user is the LatticeXP2. How- ever, the ispPAC-POWR607 Power Manager, and the MachXO™2280 are also important to the overall operation of the board. USB Download Cable The evaluation board has a download cable built in. The components for the built-in download cable are located in the southeast corner of the board ...
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... LatticeXP2 FPGA. The serial output from the USB cable/J34 is routed directly to the serial input of the LatticeXP2 FPGA. The serial output from the LatticeXP2 is routed to J29. A jumper on J29 directs the serial output of the LatticeXP2 back to the USB cable/J34. This is the factory default configuration and is expected to be the pri- mary JTAG mode for most users. ...
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... The LatticeXP2 can also be configured to act as a slave device, and accept bitstream data from an external master. The master can be connected to either the JTAG port can be connected to the SPI interface. The LatticeXP2 Standard Evaluation Board provides a 1x10 header, J11, that permits an off-chip SPI master to program the LatticeXP2 FPGA ...
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... In the northwest corner of the board is a set of eight green 0603 form factor LEDs. These LEDs are connected to IO pins dedicated to driving the LEDs. Table 6 shows the LatticeXP2 I/O pins that control each LED. The LEDs illu- minate when the corresponding I/O is driven to V ...
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... LatticeXP2 Standard Evaluation Board provides a built-in oscillator that provides a reference frequency for syn- chronous FPGA logic. Reference frequencies can be applied to other LatticeXP2 clock inputs as well. The LatticeXP2 board provides a low-voltage (3.3V) DIP oscillator. The oscillator is installed in a 14-pin DIP socket. The socket permits the use of either a half-size or full-size DIP oscillator. ...
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... J25 J26 J27 Power Supplies and Supply Control The LatticeXP2 Standard Evaluation Board operates from input voltage. The input voltage is supplied via J9, a coaxial DC input jack. The following components operate using the 5V input: • ispPAC-POWR607 Power Manager • Bellnix DC/DC converters ...
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... adjustable supply with a range from 1.1V through 2.5V. The voltage from this supply is only routed to J12. J12 is used to configure the I/O voltage used by Bank fixed 3.3V supply. It provides 3.3V to all of the ICs on the board, as well as the LatticeXP2’s VCCAUX and VCCIO banks (except Bank 6). The 3.3V provided to VCCAUX and VCCIO pass through R17 mOhm current sense resistor ...
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... CTS RTS The LatticeXP2 FPGA is connected to the RS232 DB9 connector using a Max 3232 buffer chip. This buffer permits the LatticeXP2 3.3V I/O pins to be interfaced to the 12V RS232 signaling standard. The LatticeXP2 I/O pins that connect to the RS232 buffer listed in Table 13. ...
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... CF20 CF21 CF22 Mixed Signal Support The LatticeXP2 Standard Evaluation Board also provides access to some mixed signal interface chips. There are four primary components dedicated to performing mixed signal functions on the evaluation board. These compo- nents are: • 12-bit Analog to Digital Converter • ...
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... A/D inputs. The remaining three inputs are not connected to any passive or active components. These test points can be used to inject signals meeting your own test requirements. The digital I/O side of the device connects directly to the LatticeXP2 FPGA. Twelve of the I/O are the data-bus pins, and seven are used to access the internal registers. ...
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... AB9 D9 AA8 D10 AB8 D11 AA7 D12 AB7 D13 AA6 Ordering Part Number LFXP2-17E-L-EV 15 LatticeXP2 Standard Evaluation Board User’s Guide ) and a clock transition occurs, the IL SRAM Function LatticeXP2 I/O D14 AB6 D15 AB5 D16 W14 D17 Y15 D18 W15 D19 ...
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... February 2010 © 2010 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. Version 01 ...
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... Lattice Semiconductor Appendix A. Schematics Figure 4. LatticeXP2 Standard Evaluation Board LatticeXP2 Standard Evaluation Board User’s Guide 17 ...
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... Lattice Semiconductor Figure 5. LatticeXP2 Power and Configuration LatticeXP2 Standard Evaluation Board User’s Guide NC2 U19 NC1 H8 18 ...
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... Lattice Semiconductor Figure 6. LatticeXP2 Banks Evaluation Board User’s Guide 2 2 BANK BANK 3 3 BANK BANK 0 0 BANK BANK 1 1 BANK BANK 19 LatticeXP2 Standard ...
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... Lattice Semiconductor Figure 7. LatticeXP2 Banks Evaluation Board User’s Guide 6 6 BANK BANK 7 7 BANK BANK 4 4 BANK BANK 5 5 BANK BANK 20 LatticeXP2 Standard ...
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... Lattice Semiconductor Figure 8. LatticeXP2 Programming Interfaces CL10 CL9 DON_1 CL8 DON_0 LatticeXP2 Standard Evaluation Board User’s Guide 2 1 TCK_DN ...
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... Lattice Semiconductor Figure 9. LatticeXP2 Bypass Capacitors LatticeXP2 Standard Evaluation Board User’s Guide 22 ...
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... Lattice Semiconductor Figure 10. Peripherals and Clock Inputs LatticeXP2 Standard Evaluation Board User’s Guide 23 ...
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... Lattice Semiconductor Figure 11. D/A, A/D, 7-Segment and RS232 2 1 LatticeXP2 Standard Evaluation Board User’s Guide ...
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... Lattice Semiconductor Figure 12. Compact Flash, LVDS, Switches and LCD LatticeXP2 Standard Evaluation Board User’s Guide ...
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... Lattice Semiconductor Figure 13. Asynchronous SRAM CY7C1021CV33 CY7C1021CV33 - - 64Kx16 64Kx16 CY7C1021CV33 CY7C1021CV33 - - CY7C1011CV33 CY7C1011CV33 - - 128Kx16 128Kx16 CY7C1011CV33 CY7C1011CV33 - - CY7C1041CV33 CY7C1041CV33 - - 256Kx16 256Kx16 CY7C1041CV33 CY7C1041CV33 - - 26 LatticeXP2 Standard Evaluation Board User’s Guide 64Kx16 64Kx16 128Kx16 128Kx16 256Kx16 256Kx16 ...
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... Lattice Semiconductor Figure 14. Prototype Grid LatticeXP2 Standard Evaluation Board User’s Guide 27 ...
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... Lattice Semiconductor Figure 15. Power Manager LatticeXP2 Standard Evaluation Board User’s Guide 28 ...
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... Lattice Semiconductor Figure 16. 1.2V Core Supply COMP 6 GND 4 29 LatticeXP2 Standard Evaluation Board User’s Guide ...
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... Lattice Semiconductor Figure 17. 3.3V Power Converter COMP 6 GND 4 30 LatticeXP2 Standard Evaluation Board User’s Guide ...
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... Lattice Semiconductor Figure 18. Adjustable Power Supply COMP 6 GND 4 31 LatticeXP2 Standard Evaluation Board User’s Guide ...
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... Lattice Semiconductor Figure 19. USB Download PHY AVCC 14 AVCC 10 VCC 50 VCC 39 VCC 34 VCC 24 VCC 18 VCC 6 Evaluation Board User’s Guide AGND 17 AGND 13 GND 48 GND 35 GND 33 GND 19 GND 7 GND 4 32 LatticeXP2 Standard ...
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... Lattice Semiconductor Figure 20. MachXO Power LatticeXP2 Standard Evaluation Board User’s Guide 33 ...
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... Lattice Semiconductor Figure 21. MachXO Banks LatticeXP2 Standard Evaluation Board User’s Guide PT5B/PT6F/PT9B/CLK0 D7 XOBank01_2 PT5A/PT6E/PT9A D8 XOBank01_1 34 ...
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... Lattice Semiconductor Figure 22. MachXO Banks LatticeXP2 Standard Evaluation Board User’s Guide PB5D/PB6F/PB9B P8 XOBank45_1 PB5C/PB6E/PB9A P7 XOBank45_0 35 ...
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... Lattice Semiconductor Figure 23. Placement Proposal RS232 ADS7842 rs232 soic8 soic16 dip14 Sense Sense Socket CF Sense Sense Sense SMA 7seg soic8 SMA 36 LatticeXP2 Standard Evaluation Board User’s Guide 68013A 1 PWR ...