LFXP2-17E-L-EVN Lattice, LFXP2-17E-L-EVN Datasheet - Page 11

• Manufacturer Part Number: LFXP2-17E-L-EVN
• Description: MCU, MPU & DSP Development Tools LatticeXP2 Eval Board Standard
• Manufacturer: Lattice

Specifications of LFXP2-17E-L-EVN

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
• LCD Display, contrast and backlight controls
ispPAC-POWR607
The ispPAC-POWR607 is a low-cost power management chip that is used on the LatticeXP2 Standard Evaluation
Board to turn on the DC/DC converters in a controlled sequence. The LatticeXP2 FPGA does not require voltages
to be applied in a predefined sequence. The ispPAC-POWR607 permits testing any startup sequence.
The ispPAC-POWR607 operates over a much looser DC input range than most 3.3V logic. It is capable of running
from an input supply less than 3.96V and greater than 2.64V. This allows the DC regulation from the 5V input to be
performed with loose tolerances and inexpensive components.
The evaluation board uses a zener diode and a transistor to regulate the 5V input. The ispPAC-POWR607 is the
first device on the board to have a stable supply voltage. Using this stable supply voltage it is able to turn on other
supplies in a controlled sequence. The sequence is reprogrammable. Reprogramming is done using Lattice Semi-
conductor’s PAC Designer
factory default program is available on the Lattice web site at www.latticesemi.com/boards. Navigate to the appro-
priate page for this board and choose “Design Files” from the list of available resources.
The ispPAC-POWR607 sequence programmed from the factory starts by enabling the 1.2V DC converter. The
Power Manager waits for the 1.2V supply rail to reach 95% of its threshold voltage before turning on any other sup-
ply. The next voltage supply to be enabled is the 3.3V rail. Once again the Power Manager waits for this rail to
reach 95% threshold. When the 3.3V rail reaches threshold, the adjustable voltage rail is enabled, but the Power
Manager does not wait for it to reach a specified threshold since this rail is an auxiliary supply rail. The next step is
for the Power Manager to monitor the PWDN/IN1 input pin. When this pin goes to V
all of the DC/DC converters.
When the IN1 pin returns to V
Table 10. ispPAC-POWR607 to LatticeXP2 General Purpose Connections
Bellnix DC/DC Converters
The 5V rail also supplies power to Bellnix DC/DC converters. The Bellnix converters are point of load (POL) DC
supplies. The supplies are mounted close to the LatticeXP2 FPGA in order to increase response time during peri-
ods of high current demand.
U3 is solely dedicated to supplying the LatticeXP2 FPGA’s core voltage. The 1.2V passes through R12, a 10mOhm
current sense resistor. The resistor permits voltage drop measurements to be used to determine how much power
is being used by the LatticeXP2.
U5 is an adjustable supply with a range from 1.1V through 2.5V. The voltage from this supply is only routed to J12.
J12 is used to configure the I/O voltage used by Bank 6.
U6 is a fixed 3.3V supply. It provides 3.3V to all of the ICs on the board, as well as the LatticeXP2’s VCCAUX and
VCCIO banks (except Bank 6). The 3.3V provided to VCCAUX and VCCIO pass through R17, a 10 mOhm current
sense resistor. This allows for a voltage drop measurement to be taken indicating the amount of current being
drawn by the LatticeXP2.
®
software, available from www.latticesemi.com/pac-designer. The source code for the
IL
the Power Manager starts over as if power had just been applied.
ispPAC-POWR607 Pin
28
26
23
22
20
11
LatticeXP2 I/O
M19
M20
V19
P19
R19
Evaluation Board User’s Guide
IH
the Power Manager disables
LatticeXP2 Standard