LFXP2-17E-L-EVN Lattice, LFXP2-17E-L-EVN Datasheet - Page 8

• Manufacturer Part Number: LFXP2-17E-L-EVN
• Description: MCU, MPU & DSP Development Tools LatticeXP2 Eval Board Standard
• Manufacturer: Lattice

Specifications of LFXP2-17E-L-EVN

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Push-Buttons and Status LEDs
There are four push-buttons and three LEDs on the south edge of the evaluation board. Switch SW2 and SW3, the
westernmost, are routed to generic LatticeXP2 I/Os. One of these buttons typically acts as a reset switch, providing
a reset pulse to logic inside the LatticeXP2.
SW4, which is near the USB connector, is tied to the LatticeXP2’s PROGRAMn input. Pressing this switch will
cause the LatticeXP2 to reprogram itself, as long as CFG0 is set to V
SW5 is adjacent to SW4 and is the reset button for the built-in USB download cable. Pressing this button will cause
the USB cable to re-enumerate with the USB hub.
In the southeast corner of the board are three status LEDs. These indicate the state of the LatticeXP2’s Done,
INITn, and PROGRAMn I/O pins. During normal operation the Done and the INITn LEDs will illuminate.
Global Output Enable
The LatticeXP2 has a global output enable control. The GOE is routed to J15, and the factory default setting on J15
is to enable the LatticeXP2 outputs. The jumper on J15 can be moved from the default setting (open) to disable (tri-
state) all of the LatticeXP2 I/Os.
Table 4. Global Output Enable
Prototype Grid
The board provides a small 100mil center-center prototype area. The prototype area has a set of plated through-
holes in a 5x8 pattern. There are a total of 16 I/O pins connected in the prototype area. The topmost row is a series
of eight horizontal plated through-holes connected to the ground plane. South of this row is a row of plated through-
holes connected to the LatticeXP2 device. The rows alternate GND/signal/GND/signal/GND from north to south.
Some of the plated through-holes are connected to LatticeXP2 Bank 6. It is possible to modify the I/O voltage on
Bank 6 using J12.
Table 5. Testpoint Connections
LED Displays
In the northwest corner of the board is a set of eight green 0603 form factor LEDs. These LEDs are connected to
IO pins dedicated to driving the LEDs. Table 6 shows the LatticeXP2 I/O pins that control each LED. The LEDs illu-
minate when the corresponding I/O is driven to V
Bank #
Jumper Block
6
6
6
6
6
3
3
3
Open*
Shunt
J15
LatticeXP2 I/O
W22
U20
U21
U2
R3
N2
T3
P4
Outputs disabled (tri-state)
Outputs enabled
OL
.
Output Enable State
8
Bank #
6
6
6
6
6
3
3
3
IL
.
LatticeXP2 I/O
Evaluation Board User’s Guide
W20
V20
V22
U3
R4
M3
M4
V3
LatticeXP2 Standard