PAC-SYSCLK5620AV Lattice, PAC-SYSCLK5620AV Datasheet

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PAC-SYSCLK5620AV

Manufacturer Part Number
PAC-SYSCLK5620AV
Description
MCU, MPU & DSP Development Tools ispCLK5620AV Design System
Manufacturer
Lattice
Datasheet

Specifications of PAC-SYSCLK5620AV

Processor To Be Evaluated
ispClock5620A
Silicon Manufacturer
Lattice
Silicon Core Number
IspPAC-CLK5620AV-01T100I
Kit Contents
IspClock5620A Evaluation Board, IspDownLoad Cable, AC Adapter, User Documentation
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
ispClock5620A Evaluation Board:
ispPAC-CLK5620A-EV1
March 2007
Application Note AN6072
Introduction
The Lattice Semiconductor ispClock™5620A In-System-Programmable Analog Circuit allows designers to imple-
ment clock distribution networks supporting multiple, synchronized output frequencies using a single integrated cir-
cuit.
By integrating a Phase-Locked Loop (PLL) along with multiple output dividers, the ispClock5620A can derive up to
five separate output frequencies from a single input reference frequency. To facilitate the implementation of wide-
fanout clock trees, the ispClock5620A provides up to 20 single-ended outputs or 10 differential outputs, organized
as ten banks of two. Each output bank may be independently programmed to support different logic standards and
operating options. Additionally, each single-ended output or differential output may be skew-adjusted to compen-
sate for the effects of propagation delay along the PCB traces used in the distribution network. All configuration
2
®
data is stored internally in E
CMOS
non-volatile memory. Programming a configuration is accomplished through
an industry-standard JTAG IEEE 1149.1 interface.
Figure 1. ispPAC-CLK5620A-EV1 Evaluation Board
ispPAC-CLK5620A-EV1 Evaluation Board
The ispPAC-CLK5620A-EV1 evaluation board (Figure 1) allows the designer to quickly configure and evaluate the
ispClock5620A on a fully assembled printed-circuit board. The four-layer board supports a 100-pin TQFP package,
© 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
1
an6072_01.1

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PAC-SYSCLK5620AV Summary of contents

Page 1

... The ispPAC-CLK5620A-EV1 evaluation board (Figure 1) allows the designer to quickly configure and evaluate the ispClock5620A on a fully assembled printed-circuit board. The four-layer board supports a 100-pin TQFP package, © 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifi ...

Page 2

... To simplify evaluation work, the ispPAC-CLK5620A-EV1 board was designed to operate from a single 4.5V-5.5V power supply, which may be brought in through either a pair of banana plugs (J2 and J3 standard 5mm power plug (J1 - center tip positive). The evaluation board provides two linear regulators to provide the appropriate operat- ing voltages for the ispClock5620A. One of these regulators provides a fi ...

Page 3

... CMOS logic control signals applied to the J5 header connector to over-ride the on-board switch set- tlings. Position Function (when ON) 1 PLL_BYPASS 2 PS0 3 PS1 4 GOE 5 SGATE 6 REFSEL 7 OEX 8 OEY 9 OSC DIS 10 11 BANK8 and BANK9 VCCO Programming 12 3 ispClock5620A Evaluation Board: ispPAC-CLK5620A-EV1 ...

Page 4

... Finally, when LED D4 (green) is lit, this indicates that the ispClock5620A’s PLL ‘locked’ state. Schematics The following three figures comprise the schematics for the ispPAC-CLK5620A-EV1 evaluation board. Figure 3 shows the on-board power-conditioning circuitry, Figure 4 shows the high-speed interconnects and on-board oscil- lator circuitry, while Figure 5 shows all the logic control signals and indicators ...

Page 5

... R16 1K R17 1K R18 1K R19 1K R20 1K R21 1K R22 1K R23 1K V33 R26 680 LOCK R15 R24 680 2.2K POWER R6 1K R25 680 5 ispClock5620A Evaluation Board: ispPAC-CLK5620A-EV1 V33 C11 0.1u V33 FB1 30 VCCA 31 C9 GNDA 0.1u VCCO FB3 67 VCCO9 C13 U1 70 GNDO9 0.1u 69 BANK9A ...

Page 6

... Lattice Semiconductor PCB Artwork Figure 6. Silk Screen Figure 7. Component Side Copper (Layer 1) ispClock5620A Evaluation Board: ispPAC-CLK5620A-EV1 6 ...

Page 7

... Lattice Semiconductor Figure 8. Ground Plane (Layer 2) Figure 9. Power Plane (Layer 3) ispClock5620A Evaluation Board: ispPAC-CLK5620A-EV1 7 ...

Page 8

... Lattice Semiconductor Figure 10. Solder-side Copper (Layer 4) ispClock5620A Evaluation Board: ispPAC-CLK5620A-EV1 8 ...

Page 9

... Momentary Tactile Switch, Panasonic EVQPAD04M 12-position dipswitch, CTS 206-12ST ispClock5620A (ispPAC-CLK5620AV-01T100I) 3.3V fixed regulator SOIC8, Texas Instruments TPS77733D Adjustable regulator SOIC8, Texas Instruments TPS77701D 100MHz LVCMOS Oscillator, ECS-3953M-1000-B Rubber Feet, 3M SJ-5003 Ordering Part Number PAC-SYSCLK5620AV ® Cable. 9 ispClock5620A Evaluation Board: ispPAC-CLK5620A-EV1 Description China RoHS Environment-Friendly ...

Page 10

... Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. Version 01.0 Initial release. 01.1 Added Ordering Information section. 10 ispClock5620A Evaluation Board: ispPAC-CLK5620A-EV1 Change Summary ...

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