C8051F206DK-G Silicon Laboratories Inc, C8051F206DK-G Datasheet - Page 91

• Manufacturer Part Number: C8051F206DK-G
• Description: MCU, MPU & DSP Development Tools MCU DEVELOPMENT KIT W/ GLOBAL POWER SPLY
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051F206DK-G

• Processor To Be Evaluated: C8051F206
• Data Bus Width: 8 bit
• Interface Type: USB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12. Reset Sources
The reset circuitry of the MCU allows the controller to be easily placed in a predefined default condition.
On entry to this reset state, the CIP-51 halts program execution, forces the external port pins to a known
state and initializes the SFRs to their defined reset values. Interrupts and timers are disabled. On exit, the
program counter (PC) is reset, and program execution starts at location 0x0000.
All of the SFRs are reset to predefined values. The reset values of the SFR bits are defined in the SFR
detailed descriptions. The contents of internal data memory are not changed during a reset and any previ-
ously stored data is preserved. However, since the stack pointer SFR is reset, the stack is effectively lost
even though the data on the stack are not altered.
The I/O port latches are reset to 0xFF (all logic ones), activating internal weak pull-ups which take the
external I/O pins to a high state. The weak pull-ups are enabled during and after the reset. If the source of
reset is from the V
V
On exit from the reset state, the MCU uses the internal oscillator running at 2MHz as the system clock by
default. Refer to Section 13 for information on selecting and configuring the system clock source. The
Watchdog Timer is enabled using its longest timeout interval. (Section 12.7 details the use of the Watch-
dog Timer.) Once the system clock source is stable, program execution begins at location 0x0000.
There are six sources for putting the MCU into the reset state: power-on/power-fail (V
RST pin, software commanded, Comparator 0, Missing Clock Detector, and Watchdog Timer. Each reset
source is described below:
DD
CP0+
CP0-
reset timeout.
System
DD
Clock
Monitor or writing a '1' to the PORSF bit, the RST pin is driven low until the end of the
Comparator 0
+
-
Detector
Missing
Clock
EN
Figure 12.1. Reset Sources Diagram
C0RSEF
EN
WDT
PRE
Rev. 1.6
VDD
CIP-51
Core
(Software Reset)
SWRSF
MonEn
Supply
Monitor
+
-
System Reset
Timeout
Supply
Reset
(wired-OR)
C8051F2xx
Reset
Funnel
DD
monitor), external
/RST
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