APA-ISP-DEMO Actel, APA-ISP-DEMO Datasheet - Page 60
APA-ISP-DEMO
Manufacturer Part Number
APA-ISP-DEMO
Description
MCU, MPU & DSP Development Tools ProAsic Plus
Manufacturer
Actel
Datasheet
1.APA075-FGG144.pdf
(178 pages)
Specifications of APA-ISP-DEMO
Processor To Be Evaluated
APA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Predicted Global Routing Delay
Table 2-43 • Worst-Case Commercial Conditions
Table 2-44 • Worst-Case Military Conditions
Global Routing Skew
Table 2-45 • Worst-Case Commercial Conditions
Table 2-46 • Worst-Case Commercial Conditions
2 -5 0
Parameter
t
t
t
t
Notes:
1. The timing delay difference between tile locations is less than 15 ps.
2. Highly loaded row 50%.
3. Minimally loaded row.
Parameter
t
t
t
t
Note: * The timing delay difference between tile locations is less than 15 ps.
Parameter
t
t
Parameter
t
t
RCKH
RCKL
RCKH
RCKL
RCKH
RCKL
RCKH
RCKL
RCKSWH
RCKSHH
RCKSWH
RCKSHH
ProASIC
PLUS
V
V
V
V
DDP
DDP
DDP
DDP
Flash Family FPGAs
= 3.0 V, V
= 3.0V, V
= 3.0 V, V
= 3.0V, V
Maximum Skew Low to High
Maximum Skew High to Low
Input Low to High
Input High to Low
Input Low to High
Input High to Low
Description
Input Low to High (high loaded row of 50%)
Input High to Low (high loaded row of 50%)
Input Low to High (minimally loaded row)
Input High to Low (minimally loaded row)
Maximum Skew Low to High
Maximum Skew High to Low
DD
DD
DD
DD
= 2.3V, T
= 2.3V, T
= 2.3 V, T
= 2.3 V, T
J
J
2
2
3
3
J
= 125°C for Military/MIL-STD-883
J
= 125°C for Military/MIL-STD-883
= 70°C
= 70°C
Description
Description
Description
1
v5.9
Max.
Max.
Std.
0.8
1.1
1.0
0.8
1.1
1.0
0.8
0.8
Max.
Std.
270
270
Max.
270
270
Units
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
Units
ps
ps
ps
ps
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