APA-EVAL-KIT Actel, APA-EVAL-KIT Datasheet
APA-EVAL-KIT
Specifications of APA-EVAL-KIT
Related parts for APA-EVAL-KIT
APA-EVAL-KIT Summary of contents
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... PLUS® ProASIC Flash Family FPGAs Features and Benefits High Capacity Commercial and Industrial • 75,000 to 1 Million System Gates • 198 Kbits of Two-Port SRAM • 712 User I/Os Military • 300, 000 to 1 Million System Gates • 198 Kbits of Two Port SRAM • ...
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... PLUS ProASIC Flash Family FPGAs Ordering Information _ APA1000 FG Speed Grade Blank = Standard Speed Part Number APA075 = 75,000 Equivalent System Gates APA150 = 150,000 Equivalent System Gates APA300 = 300,000 Equivalent System Gates APA450 = 450,000 Equivalent System Gates APA600 = 600,000 Equivalent System Gates APA750 ...
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... APA300 158 APA450 158 5 APA600 158 APA750 158 5 APA1000 158 Notes: 1. Package Definitions: TQFP = Thin Quad Flat Pack, PQFP = Plastic Quad Flat Pack, PBGA = Plastic Ball Grid Array, FBGA = Fine Pitch Ball Grid Array, CQFP = Ceramic Quad Flat Pack, CCGA = Ceramic Column Grid Array, LGA = Land Grid Array 2. Each pair of PECL I/Os is counted as one user I/O. 3. Available in RoHS compatible packages. Ordering code is " ...
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... Package TQ100 TQ144 PQ208 BG456 FG144 FG256 FG484 FG676 FG896 FG1152 CQ208 CQ352 CG624 Note Commercial I = Industrial M = Military B = MIL-STD-883 Speed Grade and Temperature Matrix Note Commercial I = Industrial M = Military B = MIL-STD-883 iv APA075 APA150 APA300 v5.9 APA450 APA600 APA750 Std. ✓ ✓ ✓ APA1000 ...
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... PLUS The ProASIC family of devices, Actel’s second- generation family of flash FPGAs, offers enhanced performance over Actel’s ProASIC family. It combines the advantages of ASICs with the benefits of programmable devices through nonvolatile flash technology. This enables engineers to create high-density systems using existing ASIC or FPGA design flows and tools. In addition, ...
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PLUS ProASIC Flash Family FPGAs PLUS ProASIC Architecture PLUS The proprietary ProASIC architecture granularity comparable to gate arrays. PLUS The ProASIC device core consists of a Sea-of-Tiles (Figure 1-1). Each tile can be configured as a three-input logic function (e.g., ...
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... (CLK (Reset) Figure 1-3 • Core Logic Tile Live at Power-Up PLUS The Actel flash-based ProASIC Level 0 of the live at power-up (LAPU) classification standard. This feature helps in system component initialization, executing critical processor wakes up, setting up and configuring memory blocks, clock generation, and bus activity management. ...
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... The Actel products described in this advance status datasheet may not have completed Actel’s qualification process. Actel may amend or enhance products during the product introduction and qualification process, resulting in changes in device functionality or performance the responsibility of each customer to ensure the fitness of any Actel product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life- support, and other high-reliability applications. Consult Actel’ ...
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... FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-51 896-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-59 1152-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-69 624-Pin CCGA/LGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-78 Datasheet Information List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Data Sheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 Export Administration Regulations (EAR 4-8 Actel Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . 2-51 v5.9 PLUS ...
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General Description Routing Resources PLUS The routing structure of ProASIC to provide high performance through a flexible four- level hierarchy of routing resources: ultra-fast local resources, efficient long-line resources, high-speed, very long-line resources, and high performance global networks. The ultra-fast ...
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PLUS ProASIC Flash Family FPGAs Spans 4 Tiles Figure 2-2 • Efficient Long-Line Resources 2 -2 Spans 2 Tiles Spans 1 Tile ...
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... APA1000 device. Details on the clock spines and various numbers of the family are given in The flexible use of the ProASIC designer to cope with several design requirements. Users ...
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... APA150 APA300 512 768 1,024 3,072 6,144 8,192 v5.9 High-Performance Global Network Global Networks Global Pads Global Spine Global Ribs Scope of Spine (Shaded area plus local RAMs and I/Os) APA450 APA600 APA750 APA1000 1,024 1,536 2,048 12,288 21,504 32,768 2,560 56,320 ...
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... Figure 2-5 • Core Cell Coordinates for the APA1000 cells and core cells. In addition, the I/O coordinate system changes depending on the die/package combination. Core cell coordinates start at the lower left corner (represented as (1,1 (1,5) if memory blocks are present at the bottom ...
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... This input type may be slower than a standard input under certain conditions and has a typical hysteresis of 0.35 V. I/O macros with an "S" in the standard I/O library have added Schmitt capabilities. • 3.3 V PCI Compliant (except Schmitt trigger inputs) • ...
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... DD PLUS V on ProASIC devices. Failure to follow these DDP guidelines may result in undesirable pin behavior during system start-up. For more information, refer to Actel’s PLUS Power-Up Behavior of ProASIC note. LVPECL Input Pads In addition to standard I/O pads and power pads, PLUS ProASIC ...
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... Boundary-Scan Opcodes EXTEST SAMPLE/PRELOAD IDCODE 2 -8 pins are dedicated for boundary-scan test usage. Actel recommends that a nominal 20 kΩ pull-up resistor is added to TDO and TCK pins. The TAP controller is a four-bit state machine (16 states) that operates as shown in 1s and 0s represent the values that must be present at TMS at a rising edge of TCK for the given state transition 2-9) ...
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The TAP controller receives two control inputs (TMS and TCK) and generates control and clock signals for the rest of the test logic architecture. On power-up, the TAP controller enters the Test-Logic-Reset state. To guarantee a reset of the controller ...
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... PLUS ProASIC Clock Management System PLUS ProASIC devices provide designers with very flexible clock conditioning capabilities. Each member of the PLUS ProASIC family contains two phase-locked loop (PLL) blocks which perform the following functions: • Clock Phase Adjustment via Programmable Delay (250 ps steps from – ns) • ...
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The clock conditioning circuit can advance or delay the clock (in increments of 0.25 ns) relative to the positive edge of the incoming reference clock. The system also allows for the selection of output frequency clock ...
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... Phase Shift Clock by 0° Global MUX Configuration Tile Configuration Tile CORE DATA Signals to the Global MUX Control Signals to the Global MUX PLUS Clock Conditioning Circuitry Datapath –0.25 to – 0.25 ns increments Fixed delay of –2.95 ns GLB +0. 0.25 ns increments GLA +0. 0.25 ns increments v5.9 Global MUX B OUT ...
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... The shift register can be accessed either from user logic within the device or via the JTAG port. Another option is internal dynamic configuration hardware. Refer to Actel's ProASIC Reconfiguration Using JTAG application note for more information. For information on the clock conditioning circuit, refer PLUS to Actel’ ...
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PLUS ProASIC Flash Family FPGAs Global MUX B OUT 33 MHz External Feedback Global MUX A OUT Figure 2-13 • Using the PLL 33 MHz In, 133 MHz Out Global MUX B OUT 40 MHz External Feedback Global MUX A ...
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Global MUX B OUT 133 MHz External Feedback Global MUX A OUT Figure 2-15 • Using the PLL to Delay the Input Clock Global MUX B OUT 133 MHz External Feedback Global MUX A OUT Figure 2-16 • Using the ...
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PLUS ProASIC Flash Family FPGAs On-Chip Off-Chip Global MUX B OUT 133 MHz External Feedback Global MUX A OUT Reference Clock Figure 2-17 • Using the PLL for Clock Deskewing 180° ÷n PLL Core 0° ÷m ...
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... The derating factors shown in should be applied to all timing data contained within this datasheet. All timing numbers listed in this datasheet represent sample timing characteristics of ProASIC Actual timing delay values are design-specific and can be derived from the Timer tool in Actel’s Designer software after place-and-route. = 70° 2 0° ...
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PLUS ProASIC Flash Family FPGAs PLL Electrical Specifications Parameter Frequency Ranges Reference Frequency f (min.) IN Reference Frequency f (max.) IN OSC Frequency f (min.) VCO OSC Frequency f (max.) VCO Clock Conditioning Circuitry f (min.) OUT Clock Conditioning Circuitry ...
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... PLL locking is guaranteed only when using low drive strength and low slew rate I/O. PLL locking may be inconsistent when using high drive strength or high slew rate I/Os SSO APA300 APA600 APA1000 APA300 APA600 APA1000 ProASIC ≤ T –40°C J ≤ Hermetic packages 8 SSO ≤ ...
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... This protects the device from being read back and duplicated. Since programmed data is stored in nonvolatile memory cells (actually very small capacitors) rather than in the wiring, physical deconstruction cannot be used to compromise data. This type of security breach is further discouraged ...
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Table 2-13 • Basic Memory Configurations Type Write Access RAM Asynchronous RAM Asynchronous RAM Asynchronous RAM Asynchronous RAM Asynchronous RAM Asynchronous RAM Synchronous RAM Synchronous RAM Synchronous RAM Synchronous RAM Synchronous RAM Synchronous FIFO Asynchronous FIFO Asynchronous FIFO Asynchronous FIFO ...
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PLUS ProASIC Flash Family FPGAs DI <0:8> SRAM WADDR <0:7> (256x9) WRB WBLKB Sync Write WCLKS and Sync Read Ports WPE PARODD DI <0:8> SRAM WADDR <0:7> (256x9) WRB WBLKB Sync Write and WCLKS Async Read Ports WPE PARODD Note: ...
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DI<0:8> LEVEL<0:7> LGDEP<0:2> FIFO (256x9) WRB WBLKB Sync Write RDB and Sync Read RBLKB Ports PARODD WCLKS DI <0:8> LEVEL <0:7> FIFO LGDEP<0:2> (256x9) WRB WBLKB Async Write RDB and Sync Read RBLKB Ports PARODD Note: Each RAM block contains ...
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... PLUS ProASIC Flash Family FPGAs Word Depth Figure 2-20 • APA1000 Memory Block Architecture Word Width Word 256 Depth 256 256 256 1,024 words x 9 bits, 1 read, 1 write Figure 2-21 • Example Showing Memory Arrays with Different Widths and Depths Word ...
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... Additionally, Libero IDE allows users to integrate both schematic and HDL synthesis into a single flow and verify the entire design in a single environment (see Actel’s website for more information about ® IDE includes Synplify AE from Synplicity® ...
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... Using ProASIC Clock Conditioning Circuits http://www.actel.com/documents/APA_PLL_AN.pdf PLUS In-System Programming ProASIC http://www.actel.com/documents/APA_External_ISP_AN.pdf Performing Internal In-System Programming Using Actel’s ProASIC http://www.actel.com/documents/APA_Microprocessor_AN.pdf PLUS ProASIC RAM and FIFO Blocks http://www.actel.com/documents/APA_RAM_FIFO_AN.pdf White Paper Design Security in Nonvolatile Flash and Antifuse FPGAs http://www.actel.com/documents/DesignSecurity_WP.pdf User’ ...
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... Ceramic Column Grid Array (CCGA/LGA) Notes: 1. Valid for the following devices irrespective of temperature grade: APA075, APA150, and APA300 2. Valid for the following devices irrespective of temperature grade: APA450, APA600, APA750, and APA1000 3. Depopulated array 4. Full array surface of the integrated circuit (IC) and is 110° defined as shown in Θ ...
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... total dc ac where for the APA075 for the APA150 11 mW for the APA300 12 mW for the APA450 12 mW for the APA600 13 mW for the APA750 19 mW for the APA1000 P includes the static components clock storage logic Global Clock Contribution—P clock ...
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Logic-Tile Contribution—P logic P , the logic-tile component of AC power dissipation, is given by logic logic where: 1.4 μW/MHz is the average power consumption of a logic tile per MHz of its ...
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... PLUS ProASIC Flash Family FPGAs The following is an APA750 example using a shift register design with 13,440 storage tiles (Register) and 0 logic tiles. This design has one clock at 10 MHz, and 24 outputs toggling at 5 MHz. We then calculate the various components as follows: P clock ...
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... No forced ventilation cooling system is in use years after APA600-PQ208M dissipating Table 2-19 on (junction-to-ambient) in still air that the junction temperature of the FPGA will be 120°C (25% of the time) and 70°C (75% of the time). The entry ...
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PLUS ProASIC Flash Family FPGAs Table 2-19 • Military Temperature Grade Product Performance Retention Minimum Time at T Minimum Time 110°C or Below 125°C or Below 100% 90% 10% 75% 25% 90% 50% 50% 90% 75% 100% ...
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Table 2-20 • Recommended Maximum Operating Conditions Programming and PLL Supplies Parameter Condition V During Programming PP Normal Operation V During Programming PN Normal Operation I During Programming PP I During Programming PN AVDD AGND Notes: 1. Please refer to ...
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PLUS ProASIC Flash Family FPGAs Table 2-22 • DC Electrical Specifications (V Symbol Parameter V Output High Voltage OH High Drive (OB25LPH) Low Drive (OB25LPL) V Output Low Voltage OL High Drive (OB25LPH) Low Drive (OB25LPL Input High ...
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... High Drive (OB25LPH) Low Drive (OB25LPL) C I/O Pad Capacitance I/O C Clock Input Pad Capacitance CLK Notes: 1. All process conditions. Commercial/Industrial: Junction Temperature: –40 to +110°C. 2. All process conditions. Military: Junction Temperature: –55 to +150°C. 3. During transitions, the input signal may overshoot ...
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PLUS ProASIC Flash Family FPGAs Table 2-23 • DC Electrical Specifications (V Applies to Commercial and Industrial Temperature Only Symbol Parameter V Output High Voltage OH 3.3 V I/O, High Drive (OB33P) 3.3 V I/O, Low Drive (OB33L) V Output ...
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... V Low Drive C I/O Pad Capacitance I/O C Clock Input Pad Capacitance CLK Notes: 1. All process conditions. Commercial/Industrial: Junction Temperature: –40 to +110°C. 2. During transitions, the input signal may overshoot During transitions, the input signal may undershoot to –1.0 V for a limited time of no larger than 10% of the duty cycle. ...
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PLUS ProASIC Flash Family FPGAs Table 2-24 • DC Electrical Specifications (V Applies to Military Temperature and MIL-STD-883B Temperature Only Symbol Parameter V Output High Voltage OH 3.3 V I/O, High Drive, High Slew (OB33PH) 3.3V I/O, High Drive, Normal/ ...
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... V Low Drive C I/O Pad Capacitance I/O C Clock Input Pad Capacitance CLK Notes: 1. All process conditions. Military Temperature / MIL-STD-883 Class B: Junction Temperature: –55 to +125°C. 2. During transitions, the input signal may overshoot During transitions, the input signal may undershoot to –1.0 V for a limited time of no larger than 10% of the duty cycle. ...
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... V Output High Voltage OH V Output Low Voltage OL C Input Pin Capacitance (except CLK CLK Pin Capacitance CLK Notes: 1. For PCI operation, use GL33, OTB33PH, OB33PH, IOB33PH, IB33, or IB33S macro library cell only. 2. All process conditions. Junction Temperature: –40 to +110°C for Commercial and Industrial devices and –55 to +125°C for Military. ...
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Table 2-26 • AC Specifications (3.3 V PCI Revision 2.2 Operation) Symbol Parameter Condition I Switching Current High 0 < V OH(AC) 0.3V 0.7V (Test Point) V OUT I Switching Current Low V OL(AC) DDP 0.6V 0.18V (Test Point) V ...
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PLUS ProASIC Flash Family FPGAs Tristate Buffer Delays A 50% 50 PAD 50 DLH DHL Figure 2-23 • Tristate Buffer Delays Table 2-27 • Worst-Case Commercial Conditions 2.3 ...
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Table 2-29 • Worst-Case Military Conditions load, T DDP DD Macro Type Description OTB33PH 3.3 V, PCI Output Current, High Slew Rate OTB33PN 3.3 V, High Output Current, Nominal Slew ...
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PLUS ProASIC Flash Family FPGAs Output Buffer Delays A Figure 2-24 • Output Buffer Delays Table 2-31 • Worst-Case Commercial Conditions load, T DDP DD Macro Type OB33PH 3.3 V, ...
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Table 2-33 • Worst-Case Military Conditions V = 3.0V 2.3V load, T DDP DD Macro Type Description OB33PL 3.3V, High Output Current, Low Slew Rate OB33LH 3.3V, Low Output Current, High Slew Rate OB33LN 3.3V, Low ...
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PLUS ProASIC Flash Family FPGAs Input Buffer Delays PAD Figure 2-25 • Input Buffer Delays Table 2-35 • Worst-Case Commercial Conditions DDP DD Macro Type IB33 3.3 V, CMOS Input Levels ...
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Table 2-37 • Worst-Case Military Conditions V = 3.0V 2.3V, T DDP DD Macro Type Description IB33 3.3 V, CMOS Input Levels IB33S 3.3 V, CMOS Input Levels Notes Input Pad-to-Y High INYH 2. t ...
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PLUS ProASIC Flash Family FPGAs Global Input Buffer Delays Table 2-39 • Worst-Case Commercial Conditions DDP DD Macro Type GL33 3.3 V, CMOS Input Levels GL33S 3.3 V, CMOS Input Levels ...
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Table 2-41 • Worst-Case Military Conditions V = 3.0V 2.3V, T DDP DD Macro Type GL33 3.3V, CMOS Input Levels GL33S 3.3V, CMOS Input Levels PECL PPECL Input Levels Notes Input Pad-to-Y High INYH 2. ...
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PLUS ProASIC Flash Family FPGAs Predicted Global Routing Delay Table 2-43 • Worst-Case Commercial Conditions DDP DD Parameter t Input Low to High RCKH t Input High to Low RCKL t ...
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Module Delays Figure 2-26 • Module Delays Sample Macrocell Library Listing Table 2-47 • Worst-Case Military Conditions 70º Cell Name NAND2 2-Input NAND AND2 2-Input AND ...
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PLUS ProASIC Flash Family FPGAs Table 2-48 • Recommended Operating Conditions Parameter Maximum Clock Frequency* Maximum RAM Frequency* Maximum Rise/Fall Time on Inputs* • Schmitt Trigger Mode (10% to 90%) • Non-Schmitt Trigger Mode (10% to 90%) Maximum LVPECL Frequency* ...
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Table 2-50 • JTAG Switching Characteristics Description Output delay from TCK falling to TDI, TMS TDO Setup time before TCK rising TDO Hold time after TCK rising TCK period RCK period Notes: 1. For DC electrical specifications of the JTAG ...
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PLUS ProASIC Flash Family FPGAs Embedded Memory Specifications PLUS This section discusses ProASIC SRAM/FIFO embedded memory and its interface signals, including timing diagrams that show the relationships of signals as they pertain to single embedded memory blocks Table 2-13 on ...
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Synchronous SRAM Read, Access Timed Output Strobe (Synchronous Transparent) RCLKS RBD, RBLKB RADDR Note: The plot shows the normal operation status. Figure 2-28 • Synchronous SRAM Read, Access Timed Output Strobe (Synchronous Transparent) Table 2-52 • 0°C to ...
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PLUS ProASIC Flash Family FPGAs Synchronous SRAM Read, Pipeline Mode Outputs (Synchronous Pipelined) RCLKS RDB, RBLKB New Valid RADDR Address DO RPE t RACS t RACH t RDCH t RDCS Note: The plot shows the normal operation status. Figure 2-29 ...
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Asynchronous SRAM Write WADDR WRB, WBLKB DI WPE t AWRS t WPDA Note: The plot shows the normal operation status. Figure 2-30 • Asynchronous SRAM Write Table 2-54 • 0°C to 110° 2 2.7 ...
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PLUS ProASIC Flash Family FPGAs Asynchronous SRAM Read, Address Controlled, RDB=0 RADDR DO RPE Note: The plot shows the normal operation status. Figure 2-31 • Asynchronous SRAM Read, Address Controlled, RDB = 0 Table 2-55 • 0°C to ...
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Table 2-56 • 0°C to 110° 2 2.7 V for Commercial/Industrial –55°C to 150° Symbol t Description xxx New DO access from RB ↓ ORDA Old DO ...
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PLUS ProASIC Flash Family FPGAs Synchronous SRAM Write WCLKS WRB, WBLKB WADDR, DI WPE t WRCH , t WBCH t WRCS , t WBCS t DCS , t WDCS t WPCH t DCH , t WACH Note: The plot shows ...
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Synchronous Write and Read to the Same Location RCLKS DO Last Cycle Data WCLKS t WCLKRCLKH t WCLKRCLKS t OCH t OCA ↑ Note: * New data is read if WCLKS occurs before setup time. The data stored is read ...
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PLUS ProASIC Flash Family FPGAs Asynchronous Write and Synchronous Read to the Same Location RCLKS Last Cycle Data {WRB + WBLKB WRCKS t BRCLKH t OCH t OCA t DWRRCLK ↓ Note: *New data is ...
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Asynchronous Write and Read to the Same Location RB, RADDR {WRB+WBLKB} t ORDA t ORDH t RAWRS Note: The plot shows the normal operation status. Figure 2-36 • Asynchronous Write and Read to the Same Location Table ...
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PLUS ProASIC Flash Family FPGAs Synchronous Write and Asynchronous Read to the Same Location RB, RADDR DO WCLKS t ORDA t ORDH t RAWCLKS Note: The plot shows the normal operation status. Figure 2-37 • Synchronous Write and Asynchronous Read ...
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Asynchronous FIFO Full and Empty Transitions The asynchronous FIFO accepts writes and reads while not full or not empty. When the FIFO is full, all writes are inhibited. Conversely, when the FIFO is empty, all reads are inhibited. A problem ...
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PLUS ProASIC Flash Family FPGAs FULL RB Write Write Inhibited Cycle WB Figure 2-38 • Write Timing Diagram EMPTY WB Read Read Inhibited Cycle RB Figure 2-39 • Read Timing Diagram ...
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Asynchronous FIFO Read RB = (RDB+RBLKB) RDATA EMPTY EQTH, GETH t RDWRS Note: The plot shows the normal operation status. Figure 2-40 • Asynchronous FIFO Read Table 2-63 • 0°C to 110° 2 2.7 ...
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PLUS ProASIC Flash Family FPGAs Asynchronous FIFO Write WB = (WRB + WBLKB) EQTH, GETH Note: The plot shows the normal operation status. Figure 2-41 • Asynchronous FIFO Write Table 2-64 • 0°C to 110° 2.3 ...
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Synchronous FIFO Read, Access Timed Output Strobe (Synchronous Transparent) RCLK RDB RDATA RPE EMPTY FULL EQTH, GETH Note: The plot shows the normal operation status. Figure 2-42 • Synchronous FIFO Read, Access Timed Output Strobe (Synchronous Transparent) Table 2-65 • ...
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PLUS ProASIC Flash Family FPGAs Synchronous FIFO Read, Pipeline Mode Outputs (Synchronous Pipelined) RCLK RDB RDATA RPE EMPTY FULL EQTH, GETH Note: The plot shows the normal operation status. Figure 2-43 • Synchronous FIFO Read, Pipeline Mode Outputs (Synchronous Pipelined) ...
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Synchronous FIFO Write WCLKS WRB, WBLKB WPE FULL EMPTY EQTH, GETH t WRCH , t WBCH t WRCS , t WBCS Note: The plot shows the normal operation status. Figure 2-44 • Synchronous FIFO Write Table 2-67 • ...
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PLUS ProASIC Flash Family FPGAs FIFO Reset RESETB WRB/RBD WCLKS, RCLKS FULL EMPTY EQTH, GETH t ERSA , t FRSA t THRSA Notes: 1. During reset, either the enables (WRB and RBD) OR the clocks (WCLKS and RCKLS) must be ...
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... If unused, leave the pin unconnected. AVDD Analog V should and be decoupled from GND with suitable decoupling capacitors to reduce noise. For more information, refer to Actel’s Using ProASIC application note. If the clock conditioning circuitry is not used in a design, AVDD can either be left floating or tied to 2.5 V. ...
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... The solution prevents spikes from damaging the PLUS ProASIC the V and V PP capacitor with greater rating. To filter low- Programming frequency noise (decoupling), use a 4.7 µF (low ESR, <1 <Ω, tantalum greater rating) capacitor. The capacitors should be located as close to the device pins as possible (within 2 desirable). The smaller, high- frequency capacitor should be placed closer to the device pins than the larger low-frequency capacitor ...
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... Package Pin Assignments 100-Pin TQFP 100 1 Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx. ProASIC 100-Pin TQFP v5.9 PLUS Flash Family FPGAs 3-1 ...
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... NPECL2 NPECL2 64 AGND AGND 65 I/O / GL4 I/O / GL4 66 I/O / GLMX2 I/O / GLMX2 67 GND GND I/O I/O 70 I/O I/O v5.9 100-Pin TQFP Pin APA075 APA150 Number Function Function 71 I/O I/O 72 I/O I/O 73 I/O I/O 74 I/O I/O 75 GND GND DDP DDP 77 I/O I/O ...
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... TQFP 144 1 Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx. ProASIC 144-Pin TQFP v5.9 PLUS Flash Family FPGAs 3-3 ...
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... I/O 102 67 I/O 103 68 I/O 104 69 TCK 105 70 TDI 106 71 TMS 107 72 NC 108 v5.9 144-Pin TQFP Pin APA075 APA075 Function Number Function V 109 I 110 I/O PN TDO 111 I/O TRST 112 I/O RCK 113 I/O I/O 114 I/O I/O 115 ...
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... PQFP 208 1 Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx. ProASIC 208-Pin PQFP v5.9 PLUS Flash Family FPGAs 3-5 ...
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... I/O / GL1 I/O / GL1 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O v5.9 APA600 APA750 APA1000 Function Function Function GND GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ...
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... I/O GND GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O v5.9 PLUS ProASIC Flash Family FPGAs APA750 APA1000 Function Function I/O I/O I/O I/O I/O I DDP DDP GND GND I/O I/O I/O ...
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... I/O I/O I/O I/O I/O I/O I/O TCK TCK TCK TDI TDI TDI TMS TMS TMS V V DDP DDP DDP GND GND v5.9 APA600 APA750 APA1000 Function Function Function DDP DDP DDP I/O I/O I/O I/O I/O I/O I/O I/O I/O ...
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... I/O / GLMX2 I/O / GLMX2 I/O I/O I/O I/O I/O I DDP DDP DDP I/O I/O I/O I/O I/O I/O v5.9 PLUS ProASIC Flash Family FPGAs APA750 APA1000 Function Function TDO TDO TRST TRST RCK RCK I/O I/O I/O I/O I/O I/O I/O ...
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... I/O I/O I DDP DDP DDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O v5.9 APA600 APA750 APA1000 Function Function Function GND GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ...
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... I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I DDP DDP DDP v5.9 PLUS ProASIC Flash Family FPGAs APA750 APA1000 Function Function I/O I/O I/O I/O GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ...
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... Flash Family FPGAs 208-Pin CQFP No Ceramic Tie Bar Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx 208-Pin CQFP v5.9 156 155 154 153 142 141 140 139 138 137 136 135 134 108 107 106 105 ...
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... I/O / GL2 59 AGND 60 NPECL1 61 AVDD 62 63 GND 64 I/O / GL1 65 I/O 66 I/O 67 I/O 68 I/O 69 I/O 70 v5.9 PLUS ProASIC Flash Family FPGAs 208-Pin CQFP APA600 APA1000 Function Function I/O I/O I/O I/O I/O I/O I/O I/O I DDP DDP DDP GND GND GND I/O ...
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... I/O 130 I/O 131 GND 132 I/O 133 I/O 134 I/O 135 TCK 136 TDI 137 TMS 138 V 139 DDP GND 140 v5.9 208-Pin CQFP APA300 APA600 APA1000 Function Function Function TDO TDO TDO TRST TRST TRST RCK RCK RCK I/O ...
Page 99
... I/O 204 V 205 DDP V 206 DD I/O 207 I/O 208 I/O I/O v5.9 PLUS ProASIC Flash Family FPGAs 208-Pin CQFP APA600 APA1000 Function Function I/O I/O I/O I/O I/O I/O GND GND GND I/O I/O I/O I/O I/O I/O I/O I/O ...
Page 100
... Flash Family FPGAs 352-Pin CQFP Pin Ceramic Tie Bar Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx 352-Pin CQFP v5.9 264 263 262 261 223 222 221 220 219 218 217 216 215 180 179 178 177 ...
Page 101
... DDP I/O 69 I/O 70 I/O 71 I/O 72 I/O 73 I/O 74 v5.9 PLUS ProASIC Flash Family FPGAs 352-Pin CQFP APA600 APA1000 Function Function I/O / GLMX1 I/O / GLMX1 I/O / GL2 I/O / GL2 AGND AGND AVDD AVDD NPECL1 NPECL1 I/O / GL1 I/O / GL1 I/O I/O I/O I/O ...
Page 102
... DD DD I/O 140 I/O 141 I/O 142 I/O 143 I/O 144 I/O 145 I/O 146 I/O 147 V 148 DDP v5.9 352-Pin CQFP APA300 APA600 APA1000 Function Function Function GND GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ...
Page 103
... I/O 219 V 220 DDP GND 221 I/O / GL3 V 222 PPECL2 / Input PPECL2 / Input PPECL2 / Input DD v5.9 PLUS ProASIC Flash Family FPGAs 352-Pin CQFP APA600 APA1000 Function Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ...
Page 104
... I/O 290 I/O 291 I/O 292 V 293 DDP GND 294 V 295 DD DD I/O 296 v5.9 352-Pin CQFP APA300 APA600 APA1000 Function Function Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ...
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... DD GND V DDP I/O I/O I/O I/O I/O I/O I/O I GND V DDP I/O I/O I/O v5.9 PLUS ProASIC Flash Family FPGAs 352-Pin CQFP APA600 APA1000 Function Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I GND ...
Page 106
... PLUS ProASIC Flash Family FPGAs 456-Pin PBGA Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx v5.9 A1 Ball Pad Corner ...
Page 107
... DDP NC NC I/O NC I/O I/O NC I/O I/O NC I/O I/O NC I/O I/O I/O I/O I/O v5.9 PLUS ProASIC Flash Family FPGAs APA750 APA1000 Function Function V V DDP DDP DDP V V DDP DDP DDP I/O I/O I/O I/O I/O I/O I/O I/O I/O ...
Page 108
... I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O v5.9 APA750 APA1000 Function Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ...
Page 109
... I/O I/O I/O I/O I/O I/O I/O I/O NC I/O I DDP DDP I/O I/O I/O v5.9 PLUS ProASIC Flash Family FPGAs APA750 APA1000 Function Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I DDP DDP DDP I/O ...
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... I/O I/O I/O I/O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I v5.9 APA750 APA1000 Function Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I ...
Page 111
... I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O v5.9 PLUS ProASIC Flash Family FPGAs APA750 APA1000 Function Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ...
Page 112
... I/O / GL1 I/O / GL1 I/O / GL2 I/O / GL2 I/O / GL2 I/O I/O I/O I/O I/O I/O GND GND GND GND GND GND v5.9 APA750 APA1000 Function Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ...
Page 113
... GND GND GND GND GND GND GND GND GND GND GND GND GND GND v5.9 PLUS ProASIC Flash Family FPGAs APA750 APA1000 Function Function GND GND GND GND GND GND I/O / GL4 I/O / GL4 I/O I/O I/O I/O I/O I/O I/O ...
Page 114
... I/O I/O I/O GND GND GND GND GND GND GND GND GND GND GND GND I/O I/O v5.9 APA600 APA750 APA1000 Function Function Function GND GND I/O I/O I/O I/O I/O I/O I/O I/O PPECL2 / Input PPECL2 / Input I/O I/O I/O ...
Page 115
... I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O v5.9 PLUS ProASIC Flash Family FPGAs APA750 APA1000 Function Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ...
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... I/O I/O I/O I/O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O v5.9 APA750 APA1000 Function Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O I/O I/O I/O I/O I/O I/O ...
Page 117
... I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS TMS TMS TDO TDO TDO v5.9 PLUS ProASIC Flash Family FPGAs APA750 APA1000 Function Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I ...
Page 118
... I/O NC I/O TCK TCK DDP DDP NC I DDP DDP V V DDP DDP NC I/O NC I/O v5.9 APA750 APA1000 Function Function DDP DDP RCK RCK RCK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I DDP DDP I/O I/O I/O ...
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... I/O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O v5.9 PLUS ProASIC Flash Family FPGAs APA750 APA1000 Function Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ...
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... I/O I/O NC I/O NC I/O NC I/O NC I/O NC I/O TDI TDI NC I DDP DDP V V DDP DDP v5.9 APA750 APA1000 Function Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ...
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... FBGA 12 11 Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx. A1 Ball Pad Corner v5.9 PLUS ProASIC Flash Family FPGAs 3-37 ...
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... I/O F8 I/O I/O F9 I/O I/O F10 I/O I/O F11 I/O I/O F12 I/O I/O I/O I/O v5.9 144-FBGA Pin APA075 APA150 APA300 Function Function Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ...
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... TCK M9 I/O I/O M10 TDO TDO M11 I/O I/O M12 I/O I/O v5.9 PLUS ProASIC Flash Family FPGAs 144-FBGA Pin APA075 APA150 APA300 Function Function Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ...
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... PLUS ProASIC Flash Family FPGAs 256-Pin FBGA 16 15 Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx Ball Pad Corner v5 ...
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... I/O I/O E2 I/O I/O E3 I/O I/O E4 I/O I/O E5 I/O I/O E6 v5.9 PLUS ProASIC Flash Family FPGAs 256-Pin FBGA APA150 APA300 APA450 APA600 Function Function Function Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ...
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... I/O I/O J5 I/O I/O J6 I/O I DDP DDP GND GND J10 GND GND J11 GND GND v5.9 256-Pin FBGA APA150 APA300 APA450 Function Function Function GND GND GND DDP DDP DDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ...
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... DD DD N13 GND GND N14 V V DDP DDP N15 I/O I/O N16 v5.9 PLUS ProASIC Flash Family FPGAs 256-Pin FBGA APA150 APA300 APA450 APA600 Function Function Function Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ...
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... I/O I/O I/O I/O I/O TDI TDI TDO TDO GND GND I/O I/O I/O I/O v5.9 256-Pin FBGA APA150 APA300 APA450 APA600 Function Function Function Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ...
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... FBGA Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx. A1 Ball Pad Corner v5.9 PLUS ProASIC Flash Family FPGAs 3-45 ...
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... C22 V V DDP DDP D1 I/O I/O D2 I/O I I/O D4 GND GND D5 I/O I/O D6 I/O I/O v5.9 484-Pin FBGA Pin APA450 APA600 Number Function Function D7 I/O I/O D8 I/O I/O D9 I/O I/O D10 I/O I/O D11 I/O I/O D12 I/O I/O D13 I/O I/O ...
Page 131
... H19 I/O I/O H20 H21 I/O I/O H22 I/O I/O J1 I/O I/O J2 I/O I I/O J4 I/O I/O v5.9 PLUS ProASIC Flash Family FPGAs 484-Pin FBGA Pin APA450 APA600 Number Function Function J5 I/O I/O J6 I/O I/O J7 I/O I DDP DDP J9 GND GND J10 J11 ...
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... N16 I/O I/O N17 I/O I/O N18 I/O I/O N19 I/O I/O N20 NC I/O N21 I/O I/O N22 I/O I/O v5.9 484-Pin FBGA Pin APA450 APA600 Number Function Function P1 I/O I/O P2 I/O I/O P3 I/O I/O P4 I/O I/O P5 I/O I/O P6 I/O I/O P7 ...
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... I/O I/O V16 I/O I/O V17 TDI TDI V18 V19 TDO TDO V20 GND GND v5.9 PLUS ProASIC Flash Family FPGAs 484-Pin FBGA Pin APA450 APA600 Number Function Function V21 NC I/O V22 I/O I I/O W2 I/O I/O W3 I/O I/O W4 GND GND W5 I/O ...
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... AA22 GND GND AB1 GND GND AB2 GND GND AB3 V V DDP DDP AB4 I/O I 484-Pin FBGA Pin APA450 APA600 Number Function Function AB5 I/O I/O AB6 I/O I/O AB7 I/O I/O AB8 I/O I/O AB9 I/O I/O AB10 I/O I/O ...
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... FBGA Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx v5.9 PLUS ProASIC Flash Family FPGAs A1 Ball Pad Corner 3-51 ...
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... I/O I/O C14 I/O I/O C15 I/O I/O C16 I/O I/O C17 I/O I/O C18 I/O I/O v5.9 676-Pin FBGA Pin APA600 APA750 Number Function Function C19 I/O I/O C20 I/O I/O C21 I/O I/O C22 I/O I/O C23 I/O I/O ...
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... G16 I/O I/O G17 NC NC G18 I/O I/O G19 V V DDP DDP v5.9 PLUS ProASIC Flash Family FPGAs 676-Pin FBGA Pin APA600 APA750 Number Function Function G20 NC NC G21 I/O I/O G22 I/O I/O G23 I/O I/O G24 I/O I/O G25 ...
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... GND L16 GND GND L17 GND GND L18 L19 V V DDP DDP L20 NC NC v5.9 676-Pin FBGA Pin APA600 APA750 Number Function Function L21 I/O I/O L22 I/O I/O L23 I/O I/O L24 I/O I/O L25 I/O I/O L26 I/O I/O ...
Page 139
... R16 GND GND R17 GND GND R18 R19 V V DDP DDP v5.9 PLUS ProASIC Flash Family FPGAs 676-Pin FBGA Pin APA600 APA750 Number Function Function R20 NC NC R21 I/O I/O R22 I/O I/O R23 I/O I/O R24 I/O I/O R25 I/O ...
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... DDP W17 V V DDP DDP W18 V V DDP DDP W19 W20 V V DDP DDP v5.9 676-Pin FBGA Pin APA600 APA750 Number Function Function W21 I/O I/O W22 I/O I/O W23 I/O I/O W24 I/O I/O W25 I/O I/O W26 I/O I/O Y1 ...
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... I/O AC18 I/O I/O AC19 I/O I/O AC20 I/O I/O AC21 I/O I/O v5.9 PLUS ProASIC Flash Family FPGAs 676-Pin FBGA Pin APA600 APA750 Number Function Function AC22 TMS TMS AC23 RCK RCK AC24 I/O I/O AC25 I/O I/O AC26 I/O ...
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... I/O I/O AF9 I/O I/O AF10 I/O I/O AF11 I/O I/O AF12 I/O I/O AF13 I/O I 676-Pin FBGA Pin APA600 APA750 Number Function Function AF14 I/O I/O AF15 I/O I/O AF16 I/O I/O AF17 I/O I/O AF18 I/O I/O AF19 I/O ...
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... FBGA Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx. A1 Ball Pad Corner v5.9 PLUS ProASIC Flash Family FPGAs 3-59 ...
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... V V DDP DDP C6 I/O I/O C7 I/O I/O C8 I/O I/O C9 I/O I/O C10 I/O I/O v5.9 896-Pin FBGA Pin APA750 APA1000 Number Function Function C11 I/O I/O C12 I/O I/O C13 I/O I/O C14 I/O I/O C15 I/O I/O C16 I/O I/O ...
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... I/O F19 I/O I/O F20 I/O I/O F21 I/O I/O F22 I/O I/O v5.9 PLUS ProASIC Flash Family FPGAs 896-Pin FBGA Pin APA750 APA1000 Number Function Function F23 I/O I/O F24 I/O I/O F25 GND GND F26 I/O I/O F27 I/O ...
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... I/O J27 I/O I/O J28 I/O I/O J29 I/O I/O J30 I/O I/O K1 I/O I/O K2 I/O I/O K3 I/O I/O K4 I/O I/O v5.9 896-Pin FBGA Pin APA750 APA1000 Number Function Function K5 I/O I/O K6 I/O I/O K7 I/O I/O K8 I/O I I/O K10 K11 NC I/O ...
Page 147
... DD N12 GND GND N13 GND GND N14 GND GND N15 GND GND N16 GND GND v5.9 PLUS ProASIC Flash Family FPGAs 896-Pin FBGA Pin APA750 APA1000 Number Function Function N17 GND GND N18 GND GND N19 GND GND N20 N21 V V DDP ...
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... I/O T24 I/O I/O T25 I/O I/O T26 PPECL2 / Input PPECL2 / Input T27 I/O / GL4 I/O / GL4 T28 I/O / GL3 I/O / GL3 v5.9 896-Pin FBGA Pin APA750 APA1000 Number Function Function T29 AVDD AVDD T30 I/O I/O U1 I/O I/O U2 I/O I/O U3 ...
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... I/O I/O Y1 I/O I/O Y2 I/O I/O Y3 I/O I/O Y4 I/O I/O Y5 I/O I/O Y6 I/O I/O Y7 I/O I/O Y8 I/O I I/O Y10 NC I/O v5.9 PLUS ProASIC Flash Family FPGAs 896-Pin FBGA Pin APA750 APA1000 Number Function Function Y11 Y12 Y13 Y14 Y15 Y16 Y17 V V ...
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... NC I/O AC17 NC I/O AC18 NC I/O AC19 NC I/O AC20 NC I/O AC21 NC I/O AC22 NC I/O v5.9 896-Pin FBGA Pin APA750 APA1000 Number Function Function AC23 GND GND AC24 I/O I/O AC25 I/O I/O AC26 I/O I/O AC27 I/O I/O AC28 I/O I/O AC29 ...
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... GND AG1 I/O I/O AG2 AG3 I/O I/O AG4 GND GND v5.9 PLUS ProASIC Flash Family FPGAs 896-Pin FBGA Pin APA750 APA1000 Number Function Function AG5 I/O I/O AG6 I/O I/O AG7 I/O I/O AG8 I/O I/O AG9 I/O I/O AG10 ...
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... I/O I/O AK13 I/O I/O AK14 I/O I/O AK15 I/O I/O AK16 I/O I/O AK17 I/O I/O v5.9 896-Pin FBGA Pin APA750 APA1000 Number Function Function AK18 I/O I/O AK19 I/O I/O AK20 I/O I/O AK21 I/O I/O AK22 I/O I/O ...
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... FBGA Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx. A1 Ball Pad Corner v5.9 PLUS ProASIC Flash Family FPGAs 3-69 ...
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... D4 C2 GND GND D7 C5 GND GND D10 C8 I/O D11 v5.9 1152-Pin FBGA APA1000 Pin APA1000 Function Number Function GND D12 I/O I/O D13 I/O I/O D14 I/O I/O D15 I/O I/O D16 I/O I/O D17 I/O I/O D18 I/O I/O ...
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... I/O I/O H20 I/O I/O H21 I/O I/O H22 I/O I/O H23 I/O v5.9 PLUS ProASIC Flash Family FPGAs 1152-Pin FBGA Pin APA1000 Number Function H24 I/O H25 I/O H26 I/O H27 GND H28 I/O H29 I/O H30 I/O H31 V DD ...
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... M29 DDP L27 I/O M30 L28 I/O M31 L29 I/O M32 L30 I/O M33 L31 I/O M34 L32 I/O N1 v5.9 1152-Pin FBGA APA1000 Pin APA1000 Function Number Function I/O N2 I/O I/O N3 I/O GND N4 I/O GND N5 I/O I/O N6 I/O I/O N7 I/O I/O N8 ...
Page 157
... I/O U10 I/O I/O U11 I/O I/O U12 V DDP I/O U13 V DD v5.9 PLUS ProASIC Flash Family FPGAs 1152-Pin FBGA Pin APA1000 Number Function U14 GND U15 GND U16 GND U17 GND U18 GND U19 GND U20 GND U21 GND U22 ...
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... Y15 GND AA18 Y16 GND AA19 Y17 GND AA20 Y18 GND AA21 Y19 GND AA22 Y20 GND AA23 v5.9 1152-Pin FBGA APA1000 Pin APA1000 Function Number Function GND AA24 I/O V AA25 I AA26 I/O DDP I/O AA27 I/O I/O AA28 I/O I/O ...
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... I/O I/O AE32 I/O I/O AE33 NC I/O AE34 V DD I/O AF1 V DD v5.9 PLUS ProASIC Flash Family FPGAs 1152-Pin FBGA Pin APA1000 Number Function AF2 I/O AF3 GND AF4 I/O AF5 I/O AF6 I/O AF7 V DDP AF8 I/O AF9 V DD AF10 ...
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... AK8 AJ6 GND AK9 AJ7 I/O AK10 AJ8 I/O AK11 AJ9 I/O AK12 AJ10 I/O AK13 v5.9 1152-Pin FBGA APA1000 Pin APA1000 Function Number Function I/O AK14 I/O I/O AK15 I/O I/O AK16 I/O I/O AK17 I/O I/O AK18 I/O I/O ...
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... DDP GND AP22 I/O I/O AP23 GND V AP24 I/O DDP V AP25 V DDP DD I/O AP26 V DD v5.9 PLUS ProASIC Flash Family FPGAs 1152-Pin FBGA Pin APA1000 Number Function AP27 V DD AP28 V DD AP29 I/O AP30 GND AP31 GND AP32 GND AP33 NC 3-77 ...
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... PLUS ProASIC Flash Family FPGAs 624-Pin CCGA/LGA 101112131415 161718 19 20 2122 23 25 Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx Top View D A1 Corner Index Area Bottom View v5 Side View ...
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... C17 I/O I/O C18 I/O I/O C19 GND GND C20 I/O I/O C21 I/O I/O v5.9 PLUS ProASIC Flash Family FPGAs 624-Pin CCGA/LGA Pin APA600 APA1000 Number Function Function C22 I/O I/O C23 GND GND C24 C25 I/O I/O D1 I/O I/O ...
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... G20 I/O I/O G21 I/O I/O G22 I/O I/O G23 I/O I/O G24 I/O I/O G25 I/O I/O H1 I/O I/O v5.9 624-Pin CCGA/LGA Pin APA600 APA1000 Number Function Function H2 I/O I/O H3 GND GND H4 I/O I/O H5 I/O I/O H6 I/O I/O H7 I/O I/O H8 ...
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... M1 I/O I/O M2 I/O I/O M3 I/O I/O M4 AGND AGND M5 NPECL1 NPECL1 M6 I/O / GL2 I/O / GL2 v5.9 PLUS ProASIC Flash Family FPGAs 624-Pin CCGA/LGA Pin APA600 APA1000 Number Function Function M7 I/O / GLMX1 I/O / GLMX1 DDP DDP M9 GND GND M10 M11 GND GND M12 ...
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... I/O I/O R24 I/O I/O R25 I/O I/O T1 I/O I/O T2 I/O I/O T3 I/O I/O T4 I/O I/O T5 I/O I/O T6 I/O I/O T7 I/O I DDP DDP T9 GND GND v5.9 624-Pin CCGA/LGA Pin APA600 APA1000 Number Function Function T10 T11 T12 T13 T14 T15 T16 ...
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... I/O Y11 I/O I/O Y12 I/O I/O Y13 I/O I/O Y14 I/O I/O v5.9 PLUS ProASIC Flash Family FPGAs 624-Pin CCGA/LGA Pin APA600 APA1000 Number Function Function Y15 I/O I/O Y16 I/O I/O Y17 GND GND Y18 I/O I/O Y19 TCK ...
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... I/O AD14 I/O I/O AD15 I/O I/O AD16 I/O I/O AD17 I/O I/O AD18 I/O I/O AD19 I/O I/O v5.9 624-Pin CCGA/LGA Pin APA600 APA1000 Number Function Function AD20 I/O I/O AD21 I/O I/O AD22 I/O I/O AD23 AD24 GND GND ...
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... The "Temperature Grade Offerings" table grade in the following device/packages: APA300-FG144 APA300-FG256 APA600-FG256 APA600-FG484 APA600-FG676 APA1000-FG896 v5.2 90° and 270° phase shift support was removed from the datasheet. (December 2005) The "Ordering Information" section The last paragraph of the The Output Frequency Range in the The title for Table 2-19 • ...
Page 170
PLUS ProASIC Flash Family FPGAs Previous version Changes in current version (v5.9) v5.1 MIL-STD-883 was added to the datasheet. V and V were changed CCI Table 2-9 • Temperature and Voltage Derating Factors v5.0 In the "208-Pin ...
Page 171
... Figure 2-45 • FIFO Reset. Table 2-68 • 0°C to 110° was updated in the "Pin Description" was updated for the APA600 and APA1000. Please review all was updated. was updated. was updated. PLUS and ProASIC Military/Aerospace datasheets were combined. This was updated. ...
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... Information" section The "Plastic Device Resources" section PLUS The "ProASIC Table 2-2 • Array Coordinates Figure 2-5 • Core Cell Coordinates for the APA1000 Figure 2-8 • LVPECL High and Low Threshold Values The Introduction section The "Physical Implementation" section The " ...
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Previous version Changes in current version (v5.9) v2.0 The following pins have been changed in the (continued) Pin Number "144-Pin TQFP" section The following pins have been changed in the Pin Number ...
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... Routing Skew" section The "Sample Macrocell Library Listing" section The "Pin Description" section The "Recommended Design Practice for VPN/VPP" section Pin AK31 of FG1152 for the APA1000 changed to V Advance v0.6 The "Features and Benefits" section The "ProASICPLUS Product Profile" section The " ...
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Previous version Changes in current version (v5.9) Advance v0.6 The "Calculating Typical Power Dissipation" section (continued) The "Absolute Maximum Ratings*" section The "Programming, Storage, and Operating Limits" section The "Nominal Supply Voltages’ section was updated. The "Recommended Operating Conditions" section ...
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... All pinout tables have been updated, and several packages are new: 208-Pin PQFP – APA150, APA300, APA450, APA600 456-Pin PBGA – APA150, APA300, APA450, APA600 144-Pin FBGA – APA150, APA300, APA450 256-Pin FBGA – APA150, APA300, APA450, APA600 676-Pin FBGA – APA600 Advance v0.1 Figure 2-20 • APA1000 Memory Block Architecture ...
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... Fax +44 (0) 1276 607 540 Actel Japan Actel Hong Kong EXOS Ebisu Building 4F Room 2107, China Resources Building 1-24-14 Ebisu Shibuya-ku 26 Harbour Road Tokyo 150 Japan Wanchai, Hong Kong Phone +81.03.3445.7671 Phone +852 2185 6460 Fax +81.03.3445.7668 Fax +852 2185 6488 http://jp.actel.com www ...