APA-EVAL-KIT Actel, APA-EVAL-KIT Datasheet - Page 63

• Manufacturer Part Number: APA-EVAL-KIT
• Description: MCU, MPU & DSP Development Tools ProAsic Plus Eval Kit
• Manufacturer: Actel

Specifications of APA-EVAL-KIT

• Processor To Be Evaluated: APA
• Interface Type: ISP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2-50 • JTAG Switching Characteristics
Figure 2-27 • JTAG Operation Timing
Description
Output delay from TCK falling to TDI, TMS
TDO Setup time before TCK rising
TDO Hold time after TCK rising
TCK period
RCK period
Notes:
1. For DC electrical specifications of the JTAG pins (TCK, TDI, TMS, TDO, TRST), refer to
2. If RCK is being used, there is no minimum on the TCK period.
and
Table 2-24 on page 2-38
when V
TMS, TDI
DDP
TCK
TDO
= 3.3 V.
t
TCKTDI
t
t
TCK
TDOTCK
Symbol
t
t
t
t
TDOTCK
TCKTDO
v5.9
TCKTDO
TCKTDI
t
t
RCK
TCK
Table 2-22 on page 2-34
100
Min
100
–4
10
0
2
ProASIC
1,000
1,000
Max
PLUS
4
Flash Family FPGAs
when V
DDP
Unit
ns
ns
ns
ns
ns
= 2.5 V
2-53