APA-EVAL-KIT Actel, APA-EVAL-KIT Datasheet - Page 66

• Manufacturer Part Number: APA-EVAL-KIT
• Description: MCU, MPU & DSP Development Tools ProAsic Plus Eval Kit
• Manufacturer: Actel

Specifications of APA-EVAL-KIT

• Processor To Be Evaluated: APA
• Interface Type: ISP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Synchronous SRAM Read, Pipeline Mode Outputs (Synchronous Pipelined)
Note: The plot shows the normal operation status.
Figure 2-29 • Synchronous SRAM Read, Pipeline Mode Outputs (Synchronous Pipelined)
Table 2-53 • T
2 -5 6
Symbol t
CCYC
CMH
CML
OCA
OCH
RACH
RACS
RDCH
RDCS
RPCA
RPCH
ProASIC
PLUS
xxx
RDB, RBLKB
T
J
J
Flash Family FPGAs
= 0°C to 110°C; V
= 0°C to 150°C, V
Clock high phase
Clock low phase
Old DO valid from RCLKS ↑
RDB hold from RCLKS ↑
RDB setup to RCLKS ↑
Old RPE valid from RCLKS ↑
Cycle time
New DO access from RCLKS ↑
RADDR hold from RCLKS ↑
RADDR setup to RCLKS ↑
New RPE access from RCLKS ↑
RADDR
RCLKS
t RACS
RPE
DO
t RACH
t RDCH
t RDCS
Description
New Valid
DD
DD
Address
= 2.3 V to 2.7 V for Commercial/Industrial
= 2.3 V to 2.7 V for Military/MIL-STD-883
Cycle Start
t CMH
Old Data Out
t CCYC
v5.9
Min.
7.5
3.0
3.0
2.0
0.5
1.0
0.5
1.0
4.0
Old RPE Out
t CML
Max.
0.75
1.0
t OCH
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t RPCA
New Valid Data Out
New RPE Out
t OCA
t RPCH
Notes