APA-EVAL-KIT Actel, APA-EVAL-KIT Datasheet - Page 71

• Manufacturer Part Number: APA-EVAL-KIT
• Description: MCU, MPU & DSP Development Tools ProAsic Plus Eval Kit
• Manufacturer: Actel

Specifications of APA-EVAL-KIT

• Processor To Be Evaluated: APA
• Interface Type: ISP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Synchronous Write and Read to the Same Location
Note: * New data is read if WCLKS
Figure 2-34 • Synchronous Write and Read to the Same Location
Table 2-58 • T
Symbol t
CCYC
CMH
CML
WCLKRCLKS
WCLKRCLKH
OCH
OCA
Notes:
1. This behavior is valid for Access Timed Output and Pipelined Mode Output. The table shows the timings of an Access Timed Output.
2. During synchronous write and synchronous read access to the same location, the new write data will be read out if the active write
3. If WCLKS changes after the hold time, the data will be read.
4. A setup or hold time violation will result in unknown output data.
clock edge occurs before or at the same time as the active read clock edge. The negative setup time insures this behavior for WCLKS
and RCLKS driven by the same design signal.
the normal operation status.
xxx
T
J
J
= 0°C to 110°C; V
= –55°C to 150°C, V
Cycle time
Clock high phase
Clock low phase
WCLKS ↑ to RCLKS ↑ setup time
WCLKS ↑ to RCLKS ↑ hold time
Old DO valid from RCLKS ↑
New DO valid from RCLKS ↑
WCLKS
RCLKS
DO
t
t
WCLKRCLKH
WCLKRCLKS
Last Cycle Data
t
t
OCH
OCA
DD
Description
↑
DD
occurs before setup time. The data stored is read if WCLKS
= 2.3 V to 2.7 V for Commercial/Industrial
= 2.3 V to 2.7 V for Military/MIL-STD-883
t
CMH
t
CCYC
v5.9
Min.
– 0.1
7.5
3.0
3.0
7.5
t
CML
Max.
7.0
3.0
New Data*
Units
↑
ns
ns
ns
ns
ns
ns
ns
occurs after hold time. The plot shows
ProASIC
OCA/OCH displayed for
Access Timed Output
PLUS
Flash Family FPGAs
Notes
2-61