Core429-OC Actel, Core429-OC Datasheet - Page 4

• Manufacturer Part Number: Core429-OC
• Description: Microcontroller Modules & Accessories ARINC 429 Bus Interface
• Manufacturer: Actel

Specifications of Core429-OC

• Product: Microcontroller Modules
• Data Bus Width: 8 bit, 16 bit, 32 bit
• Clock Speed: 1 - 20 MHz
• Interface Type: RS-232, UART

Table 3 •
Table 4 •
Table 5 •
Core429 clock rate can be programmed to be 1, 10, 16, or
20 MHz. All the Actel families listed above easily meet
the required performance.
Core429 I/O requirements depend on the system
requirements and the external interfaces. If the core and
memory blocks are implemented within the FPGA and
the CPU interface has a bidirectional data bus, then
Memory Requirements
The number of memory blocks required differs, depending on whether each channel is configured the same or
differently.
Each Channel Configured the Same
Use
4
Family
Fusion
ProASIC3/E
ProASIC
Axcelerator
RTAX-S
Family
Fusion
ProASIC3/E
ProASIC
Axcelerator
RTAX-S
Family
Fusion
ProASIC3/E
ProASIC
Axcelerator
RTAX-S
ARINC 429 Bus Interface
EQ 1
PLUS
PLUS
PLUS
Number of memory blocks = NRx * (INT (LABEL_SIZE/X) + INT (RX_FIFO_DEPTH/Y) + NTx * INT (FIFO_DEPTH/Y),
to calculate the number of memory blocks required if each channel is configured the same.
Device Utilization for One Rx and One Tx Module
Device Utilization for 16 Rx and 16 Tx Modules
Device Utilization for Legacy Mode (2 Rx and 1 Tx)
Combinational
Combinatorial
Combinatorial
13,435
13,435
16,835
1,084
8,044
9,594
1,444
1,444
1,840
1,062
848
848
518
604
955
Cells or Tiles
Cells or Tiles
Cells or Tiles
Sequential
Sequential
Sequential
9,614
9,614
5,928
5,944
6,745
1,068
1,068
609
609
377
378
429
674
653
729
23,049
23,049
22,763
13,988
16,339
Total
Total
1,457
1,457
1,461
1,033
Total
2,512
2,512
2,514
1,608
1,791
896
v5.0
approximately 74 I/O pins are required to implement
four Rx and four Tx modules. The core will require 62
pins to implement one Rx and one Tx module.
The core has various FIFO flags available for debugging
purposes. These flags may not be needed in the final
design and this will reduce the I/O count.
Memory Blocks
Memory Blocks
Memory
Blocks
5
5
5
5
5
48
48
48
48
48
3
3
3
3
3
RTAX250S
RTAX250S
A3PE600
Device
APA150
AFS600
RTAX2000S
A3PE1500
RTAX250S
A3PE600
AFS1500
Device
APA750
AX2000
Device
APA075
AFS600
AX125
Utilization
Utilization
Utilization
18%
18%
41%
20%
42%
10%
10%
48%
44%
24%
60%
60%
69%
43%
51%
EQ 1