5M160ZM100A5N Altera, 5M160ZM100A5N Datasheet - Page 152

• Manufacturer Part Number: 5M160ZM100A5N
• Description: ALTERA
• Manufacturer: Altera
• Series: MAX® Vr

Specifications of 5M160ZM100A5N

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 7.5ns
• Voltage Supply - Internal: 1.71 V ~ 1.89 V
• Number Of Logic Elements/blocks: 160
• Number Of Macrocells: 128
• Number Of Gates: -
• Number Of I /o: 79
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 100-TFBGA
• Lead Free Status / Rohs Status: Vendor undefined / RoHS Compliant

8–6
IEEE Std. 1149.1 BST Operation Control
Figure 8–5. IEEE Std. 1149.1 TAP Controller State Machine
MAX V Device Handbook
f
MAX V devices implement the SAMPLE/PRELOAD, EXTEST, BYPASS, IDCODE, USERCODE,
CLAMP and HIGHZ IEEE Std. 1149.1 BST instructions. The length of the BST instructions
is 10 bits. These instructions are described in detail later in this chapter.
For a summary of the BST instructions and their instruction codes, refer to the
and In-System Programmability in MAX V Devices
The IEEE Std. 1149.1 TAP controller, a 16-state state machine clocked on the rising
edge of TCK, uses the TMS pin to control IEEE Std. 1149.1 operation in the device.
Figure 8–5
TMS = 1
TMS = 0
TEST_LOGIC/
RUN_TEST/
RESET
IDLE
shows the TAP controller state machine.
TMS = 0
TMS = 1
TMS = 1
TMS = 1
TMS = 0
TMS = 0
TMS = 0
TMS = 0
TMS = 1
TMS = 1
TMS = 1
CAPTURE_DR
UPDATE_DR
PAUSE_DR
SHIFT_DR
EXIT1_DR
EXIT2_DR
TMS = 0
SELECT_DR_SCAN
TMS = 0
TMS = 0
TMS = 1
TMS = 1
Chapter 8: JTAG Boundary-Scan Testing in MAX V Devices
TMS = 1
TMS = 1
TMS = 0
TMS = 1
TMS = 0
TMS = 0
TMS = 1
TMS = 0
TMS = 1
TMS = 1
chapter.
CAPTURE_IR
UPDATE_IR
PAUSE_IR
EXIT2_IR
SHIFT_IR
EXIT1_IR
SELECT_IR_SCAN
TMS = 0
IEEE Std. 1149.1 BST Operation Control
TMS = 0
TMS = 0
TMS = 1
December 2010 Altera Corporation
JTAG