5M160ZM100A5N Altera, 5M160ZM100A5N Datasheet - Page 25
5M160ZM100A5N
Manufacturer Part Number
5M160ZM100A5N
Description
ALTERA
Manufacturer
Altera
Series
MAX® Vr
Specifications of 5M160ZM100A5N
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
7.5ns
Voltage Supply - Internal
1.71 V ~ 1.89 V
Number Of Logic Elements/blocks
160
Number Of Macrocells
128
Number Of Gates
-
Number Of I /o
79
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
100-TFBGA
Lead Free Status / Rohs Status
Vendor undefined / RoHS Compliant
- Current page: 25 of 164
- Download datasheet (5Mb)
Chapter 2: MAX V Architecture
Logic Elements
December 2010 Altera Corporation
LE RAM
f
The Quartus II software automatically creates carry chain logic during design
processing, or you can create it manually during design entry. Parameterized
functions such as LPM functions automatically take advantage of carry chains for the
appropriate functions. The Quartus II software creates carry chains longer than 10 LEs
by linking adjacent LABs within the same row together automatically. A carry chain
can extend horizontally up to one full LAB row, but does not extend between LAB
rows.
Clear and Preset Logic Control
LAB-wide signals control the logic for the register’s clear and preset signals. The LE
directly supports an asynchronous clear and preset function. The register preset is
achieved through the asynchronous load of a logic high. MAX V devices support
simultaneous preset/asynchronous load and clear signals. An asynchronous clear
signal takes precedence if both signals are asserted simultaneously. Each LAB
supports up to two clears and one preset signal.
In addition to the clear and preset ports, MAX V devices provide a chip-wide reset pin
(DEV_CLRn) that resets all registers in the device. An option set before compilation in
the Quartus II software controls this pin. This chip-wide reset overrides all other
control signals and uses its own dedicated routing resources without using any of the
four global resources. Driving this signal low before or during power-up prevents
user mode from releasing clears within the design. This allows you to control when
clear is released on a device that has just been powered-up. If not set for its chip-wide
reset function, the DEV_CLRn pin is a regular I/O pin.
By default, all registers in MAX V devices are set to power-up low. However, this
power-up state can be set to high on individual registers during design entry using
the Quartus II software.
The Quartus II memory compiler can configure the unused LEs as LE RAM.
MAX V devices support the following memory types:
■
■
■
■
■
■
For more information about memory, refer to the
User
FIFO synchronous R/W
FIFO asynchronous R/W
1 port SRAM
2 port SRAM
3 port SRAM
shift registers
Guide.
Internal Memory (RAM and ROM)
MAX V Device Handbook
2–13
Related parts for 5M160ZM100A5N
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
CYCLONE II STARTER KIT EP2C20N
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 7ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Classic EPLD
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 25 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: