AD5662BRJZ-2500RL7 Analog Devices Inc, AD5662BRJZ-2500RL7 Datasheet - Page 5

• Manufacturer Part Number: AD5662BRJZ-2500RL7
• Description: Single 16bit SPI DAC Reset To Midscale
• Manufacturer: Analog Devices Inc
• Series: nanoDAC™r

Specifications of AD5662BRJZ-2500RL7

• Design Resources: 4 mA to 20 mA Process Control Loop Using AD5662 (CN0009) 16-Bit Fully Isolated Voltage Output Module Using AD5662, ADuM1401, and External Amplifiers (CN0063) 16-Bit Fully Isolated 4 mA to 20 mA Output Module Using AD5662, ADuM1401, and External Amplifiers (CN0064)
• Settling Time: 8µs
• Number Of Bits: 16
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 750µW
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: SOT-23-8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TIMING CHARACTERISTICS
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of V
V
Table 2.
Parameter
t
t
t
t
t
t
t
t
t
t
1
1
2
3
4
5
6
7
8
9
10
Maximum SCLK frequency is 30 MHz at V
1
DD
= 2.7 V to 5.5 V; all specifications T
SCLK
SYNC
V
50
13
13
13
5
4.5
0
50
13
0
DIN
DD
= 2.7 V to 3.6 V
t
8
t
10
DD
Limit at T
= 3.6 V to 5.5 V, and 20 MHz at V
DB2 3
MIN
t
4
to T
t
5
MIN
t
V
33
13
13
13
5
4.5
0
33
13
0
6
MAX
DD
, T
= 3.6 V to 5.5 V
, unless otherwise noted.
MAX
t
3
Figure 2. Serial Write Operation
t
1
t
Rev. A | Page 5 of 24
2
DD
= 2.7 V to 3.6 V.
DB0
DD
t
7
) and timed from a voltage level of (V
t
9
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Conditions/Comments
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge setup time
Data setup time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
SYNC rising edge to SCLK fall ignore
SCLK falling edge to SYNC fall ignore
IL
+ V
IH
)/2. See Figure 2.
AD5662