AD6634BBC Analog Devices Inc, AD6634BBC Datasheet - Page 50

• Manufacturer Part Number: AD6634BBC
• Description: IC,RF/Baseband Circuit,CMOS,BGA,196PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: AD6634r

Specifications of AD6634BBC

• Rohs Status: RoHS non-compliant
• Rf Type: Cellular, CDMA2000, EDGE, GPRS, GSM
• Number Of Mixers: 1
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 196-CSPBGA
• Current - Supply: -
• Frequency: -
• Gain: -
• Noise Figure: -
• Secondary Attributes: -

AD6634
address is set, External Address [0] DR0 must be the first data register
read to initiate an internal access. DR2 is only four bits wide.
Data written to the upper four bits of this register will be ignored.
Likewise reading from this register will produce only 4 LSBs.
Write Sequencing
Writing to an internal location is achieved by first writing the upper
two bits of the address to Bits 1 through 0 of the ACR. Bits 7:2 may
be set to select the channel as indicated above. The CAR is then
written with the lower eight bits of the internal address (it doesn’t
matter if the CAR is written before the ACR as long as both are
written before the internal access). Data Register 2 (DR2) and
Register 1 (DR1) must be written first because the write to data
register DR0 triggers the internal access. Data register DR0 must
always be the last register written to initiate the internal write.
Read Sequencing
Reading from the microport is accomplished in the same manner.
The internal address is set up the same way as the write. A read
from data register DR0 activates the internal read, thus register DR0
must always be read first to initiate an internal read followed
by DR1 and DR2. This provides the 8 LSBs of the internal read
through the microport (D[7:0]). Additional data registers can be
read to read the balance of the internal memory.
Read/Write Chaining
The microport of the AD6634 allows for multiple accesses while
CS is held low (CS can be tied permanently low if the microport is
not shared with additional devices). The user can access multiple
locations by pulsing the WR or RD line and changing the contents
of the external 3-bit address bus. External access to the external
registers of Table XIII is accomplished in one of two modes
using the CS, RD, WR, and MODE inputs. The access modes
are Intel nonmultiplexed mode and Motorola nonmultiplexed
mode. These modes are controlled by the MODE input
(MODE = 0 for INM, MODE = 1 for MNM). CS, RD, and WR
control the access type for each mode.
Intel Nonmultiplexed Mode (INM)
MODE must be tied Low to operate the AD6634 microprocessor
in INM mode. The access type is controlled by the user with the
CS, RD (DS), and WR (RW) inputs. The RDY (DTACK) signal
is produced by the microport to communicate to the user that an
access has been completed. RDY (DTACK) goes Low at the
start of the access and is released when the internal cycle is
complete. See the timing diagrams for both the read and write
modes in the Specifications.
Motorola Nonmultiplexed Mode (MNM)
MODE must be tied High to operate the AD6634 microproces-
sor in MNM mode. The access type is controlled by the user
with the CS, DS (RD), and RW (WR) inputs. The DTACK
(RDY) signal is produced by the microport to communicate to
the user that an access has been completed. DTACK (RDY) goes
Low when an internal access is complete and then will return High
after DS (RD) is deasserted. See the timing diagrams for both the
read and write modes in the Specifications.
SERIAL PORT CONTROL
The AD6634 has a serial port serving as a control interface apart
from the microport control interface. Serial port input pin (SDI)
can access all of the internal registers for all of the channels and
has pre-emptive access over the microport. In this manner, a single
DSP could be used to control the AD6634 over the serial port
control interface.
–50–
The serial control port uses the serial clock (SCLK). The
serial input port is self-framing as described below and allows
more efficient use of the serial input bandwidth for programming.
The beginning of a serial input frame is signaled by a Frame bit
that appears on the SDI pin. This is the MSB of the Serial Input
frame. After the frame bit has been sampled high on the falling
edge of SCLK, a state counter will start and enable an 11-bit
serial shifter four serial clock cycles later. These four SCLK cycles
represent the Don’t Care bits of the serial frame that are ignored.
After all of the bits are shifted, the serial input port will pass
along the 8-bit data and 3-bit address to the arbitration block.
The serial word structure for the SDI input is illustrated in
Figure 47. Only 15 bits are listed so that the second bit in a
standard 16-bit serial word is considered the frame bit. This is
done for compatibility with the AD6620 serial input port. The
shifting order begins with frame and shifts the address MSB first
and then the data MSB first.
Serial Port Timing Specifications
The AD6634 serial control channel can operate only in the slave
mode. Figures 44–46 indicate the required timing for each
specification.
SDI
SDI is the Serial Data Input. Serial Data is sampled on the
falling edge of SCLK. This pin is used in the serial control
mode to write the internal control registers of the AD6634.
SCLK
SCLK is a clock input and the SDI input is sampled on the
falling edge of SCLK and all outputs are switched on the rising
edge of SCLK. The maximum speed of this port is 80 MHz.
SCLK
SCLK
SCLK
CLK
Figure 45. SCLK Switching Characteristics (Divide by 1)
SDI
Figure 46. Serial Input Data Timing Requirements
Figure 44. SCLK Timing Requirements
t
DSCLKH
t
SCLKL
t
t
SCLKL
SSI
DATA
t
t
SCLKH
SCLK
t
HSI
t
SCLKH
REV. 0