AD664KPZ Analog Devices Inc, AD664KPZ Datasheet



Manufacturer Part Number
Analog Devices Inc

Specifications of AD664KPZ

Settling Time
Number Of Bits
Data Interface
Number Of Converters
Voltage Supply Source
Dual ±
Power Dissipation (max)
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
The AD664 is four complete 12-bit, voltage-output DACs on
one monolithic IC chip. Each DAC has a double-buffered input
latch structure and a data readback function. All DAC read and
write operations occur through a single microprocessor-compatible
I/O port.
The I/O port accommodates 4-, 8- or 12-bit parallel words al-
lowing simple interfacing with a wide variety of microprocessors.
A reset to zero control pin is provided to allow a user to simulta-
neously reset all DAC outputs to zero, regardless of the contents
of the input latch. Any one or all of the DACs may be placed in
a transparent mode allowing immediate response by the outputs
to the input data.
The analog portion of the AD664 consists of four DAC cells,
four output amplifiers, a control amplifier and switches. Each
DAC cell is an inverting R-2R type. The output current from
each DAC is switched to the on-board application resistors and
output amplifier. The output range of each DAC cell is pro-
grammed through the digital I/O port and may be set to unipo-
lar or bipolar range, with a gain of one or two times the reference
voltage. All DACs are operated from a single external reference.
The functional completeness of the AD664 results from the
combination of Analog Devices’ BiMOS II process, laser-trimmed
thin-film resistors and double-level metal interconnects.
1. The AD664 provides four voltage-output DACs on one chip
2. The output range of each DAC is fully and independently
3. Readback capability allows verification of contents of the in-
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
Four Complete Voltage Output DACs
Data Register Readback Feature
“Reset to Zero” Override
Multiplying Operation
Double-Buffered Latches
Surface Mount and DIP Packages
MIL-STD-883 Compliant Versions Available
Automatic Test Equipment
Process Control
Disk Drives
offering the highest density 12-bit D/A function available.
ternal data registers.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
4. The asynchronous RESET control returns all D/A outputs
5. DAC-to-DAC matching performance is specified and tested.
6. Linearity error is specified to be 1/2 LSB at room tempera-
7. DAC performance is guaranteed to be monotonic over the
8. Readback buffers have tristate outputs.
9. Multiplying-mode operation allows use with fixed or vari-
10. The AD664 is available in versions compliant with MIL-
to zero volts.
ture and 3/4 LSB maximum for the K, B and T grades.
full operating temperature range.
able, positive or negative external references.
STD-883. Refer to the Analog Devices Military Products
Databook or current AD664/883B data sheet for detailed
28-Pin DIP Package
44-Pin Package
12-Bit Quad DAC
Fax: 617/326-8703

Related parts for AD664KPZ

AD664KPZ Summary of contents

Page 1

FEATURES Four Complete Voltage Output DACs Data Register Readback Feature “Reset to Zero” Override Multiplying Operation Double-Buffered Latches Surface Mount and DIP Packages MIL-STD-883 Compliant Versions Available APPLICATIONS Automatic Test Equipment Robotics Process Control Disk Drives Instrumentation Avionics PRODUCT ...

Page 2

AD664–SPECIFICATIONS Model RESOLUTION ANALOG OUTPUT 1 Voltage Range UNI Versions BIP Versions Output Current Load Resistance Load Capacitance Short-Circuit Current ACCURACY Gain Error Unipolar Offset 3 Bipolar Zero 4 Linearity Error Linearity MIN MAX Differential Linearity Differential ...

Page 3


Page 4

AD664 FUNCTIONAL DESCRIPTION The AD664 combines four complete 12-bit voltage output D/A converters with a fast, flexible digital input/output port on one monolithic chip available in two forms, a 44-pin version shown in Figure 1a and a 28-pin ...

Page 5

Mode = UNI 000000000000 = 0 V Gain = 1 100000000000 = V 111111111111 = V 000000000000 = 0 V Gain = 2 100000000000 = V 111111111111 = 2 DEFINITIONS OF SPECIFICATIONS LINEARITY ERROR: Analog Devices defines linearity error as ...

Page 6

AD664 ANALOG CIRCUIT CONSIDERATIONS Grounding Recommendations The AD664 has two pins, designated ANALOG and DIGITAL ground. The analog ground pin is the “high quality” ground ref- erence point for the device. A unique internal design has resulted in low analog ...

Page 7

Multiplying Mode Performance Figure 6 illustrates the typical open-loop gain and phase perfor- mance of the output amplifiers of the AD664. +20 GAIN +15 +10 PHASE +5 0 10k 100k FREQUENCY – Figure 6. Gain and Phase Performance ...

Page 8

AD664 Function Load 1st Rank (data) DACA DACB DACC DACD Load 2nd Rank (data) Readback 2nd Rank (data) Reset 1 Transparent All DACs DACA DACB DACC DACD 1, 2 Mode Select 1st Rank 2nd Rank 1 Readback Mode Update 2nd ...

Page 9

Figure 10a. Preload First Rank of a DAC SYMBOL MIN (ns) MIN (ns 100 ...

Page 10

AD664 occupies the topmost eight bits of the input word. The last four bits of the input word are “don’t cares.” Figure 15 shows the format of the MODE SELECT word. The first four bits determine the gain range of ...

Page 11

Fully transparent operation can be thought simultaneous load of data from Figure 9a where replacing LS with TR causes all 4 DACs to be loaded at once. The Fully transparent mode is achieved by asserting lows on ...

Page 12

AD664 Output Loads Readback timing is tested with the output loads shown in Figure 22. Figure 22. Output Loads Asynchronous Reset Operation The asynchronous reset signal shown in Figure 23 may be asserted at any time. A minimum pulse width ...

Page 13

Figure 25a. Simple AD664 to MC6801 Interface REV. C Expansion of the scheme employed in Figure 25a results in that shown in Figure 25c. Here, two AD664s are connected to an MC6801, providing a total of eight 12-bit, software program- ...

Page 14

AD664 The schemes in Figure 25 illustrate some of the trade-offs which a designer may make when configuring a system. For example, the designer may use I/O lines instead of address bits or vice versa. This decision may be influenced ...

Page 15

IBM PC* Interface Figure 27 illustrates a simple interface between an IBM PC and an AD664. The three least significant address bits are used to select the Quad and DAC. The next two address bits are used for LS and ...

Page 16

AD664 Table III details the memory locations and addresses used by this interface. HEX 300 301 302 303 304 305 306 307 308 309 30A 30B 30C 30D 30E 30F 310 311 ...

Page 17

The following IBM PC Basic routine produces four output volt- age ramps from one AD664. Line numbers 10 through 70 de- fine the hardware addresses for the first and second ranks of DAC registers as well as the first and ...

Page 18

AD664 Simple AD664 to MC68000 Interface Figure 28 shows an AD664 connected to an MC68000. In this memory-mapped I/O scheme, the “left-justified” data is written in one 12-bit input word. Four address bits are used to perform the on-chip D/A ...

Page 19

APPLICATIONS OF THE AD664 “Tester-Per-Pin” ATE Architecture Figure 29 shows the AD664 used in a single channel of a digital test system. In this scheme, the AD664 supplies four individual output voltages. Two are provided to the V puts of ...

Page 20

AD664 Temperature l Model Range AD664JN-UNI +70 C AD664JN-BIP +70 C AD664JP +70 C AD664KN-UNI +70 C AD664KN-BIP +70 C AD664KP +70 ...

Related keywords