AD7190BRUZ-REEL Analog Devices Inc, AD7190BRUZ-REEL Datasheet - Page 23

• Manufacturer Part Number: AD7190BRUZ-REEL
• Description: 2ch UltraLow Noise 24Bit SD ADC IC.
• Manufacturer: Analog Devices Inc

Specifications of AD7190BRUZ-REEL

• Design Resources: Precision Weigh Scale Design Using AD7190 with Internal PGA (CN0102)
• Number Of Bits: 24
• Sampling Rate (per Second): 4.8k
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP (0.173", 4.40mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CON23
Chop(0)
CON15
CH7(0)
CON7
Burn(0)
Table 19. Configuration Register Bit Designations
Bit Location
CON23
CON22, CON21
CON20
CON19 to CON16
CON15 to CON8
CON7
CON6
CON5
CON4
CON3
CON2 to CON0
CON22
0(0)
CON14
CH6(0)
CON6
REFDET(0)
Chop
BUF
G2 to G0
Bit Name
REFSEL
CH7 to CH0
Burn
REFDET
U/B
Description
Chop enable bit. When the chop bit is cleared, chop is disabled. When the chop bit is set, chop is
enabled. When chop is enabled, the offset and offset drift of the ADC are continuously minimized.
However, this increases the conversion time and settling time of the ADC. For example, when FS = 96
decimal and the sinc
settling time equals 160 ms. With chop disabled, higher conversion rates are allowed. For an FS word of
96 decimal and the sinc
However, at low gains, periodic calibrations may be required to remove the offset and offset drift.
These bits must be programmed with a Logic 0 for correct operation.
Reference select bits. The reference source for the ADC is selected using these bits.
REFSEL
0
1
These bits must be programmed with a Logic 0 for correct operation.
Channel select bits. These bits are used to select which channels are enabled on the AD7190. See Table 20.
Several channels can be selected, and the AD7190 automatically sequences them. The conversion on
each channel requires the complete settling time.
When this bit is set to 1, the 500 nA current sources in the signal path are enabled. When burn = 0, the
burnout currents are disabled. The burnout currents can be enabled only when the buffer is active and
when chop is disabled.
Enables the reference detect function. When set, the NOREF bit in the status register indicates when the
external reference being used by the ADC is open circuit or less than 0.6 V maximum. The reference
detect circuitry only operates when the ADC is active.
This bit must be programmed with a Logic 0 for correct operation.
Enables the buffer on the analog inputs. If cleared, the analog inputs are unbuffered, lowering the
power consumption of the device. If set, the analog inputs are buffered, allowing the user to place
source impedances on the front end without contributing gain errors to the system. With the buffer
disabled, the voltage on the analog input pins can be from 50 mV below AGND to 50 mV above AV
When the buffer is enabled, it requires some headroom; therefore, the voltage on any input pin must be
limited to 250 mV within the power supply rails.
Polarity select bit. When this bit is set, unipolar operation is selected. When this bit is cleared, bipolar
operation is selected.
Gain select bits. Written by the user to select the ADC input range as follows:
G2
0
0
0
0
1
1
1
1
CON21
0(0)
CON13
CH5(0)
CON5
0(0)
G1
0
0
1
1
0
0
1
1
CON20
REFSEL(0)
CON12
CH4(0)
CON4
BUF(1)
4
Reference Voltage
External reference applied between REFIN1(+) and REFIN1(−).
External reference applied between the P1/REFIN2(+) and P0/REFIN2(-) pins.
G0
0
1
0
1
0
1
0
1
filter is selected, the conversion time with chop enabled equals 80 ms and the
4
filter selected, the conversion time is 20 ms and the settling time is 80 ms.
Rev. B | Page 23 of 40
Gain
1
Reserved
Reserved
8
16
32
64
128
CON19
0(0)
CON11
CH3(0)
CON3
U/B (0)
ADC Input Range (5 V Reference, Bipolar Mode)
±5 V
±625 mV
±312.5 mV
±156.2 mV
±78.125 mV
±39.06 mV
CON18
0(0)
CON10
CH2(0)
CON2
G2(1)
CON17
0(0)
CON9
CH1(0)
CON1
G1(1)
CON16
(0)
CON8
CH0(1)
CON0
G0(1)
AD7190
DD
.