AD7394ARZ Analog Devices Inc, AD7394ARZ Datasheet - Page 4

• Manufacturer Part Number: AD7394ARZ
• Description: X2, 12-Bit, +3V UPwr DAC
• Manufacturer: Analog Devices Inc

Specifications of AD7394ARZ

• Settling Time: 60µs
• Number Of Bits: 12
• Data Interface: Serial
• Number Of Converters: 2
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 1mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Number Of Channels: 2
• Resolution: 12b
• Conversion Rate: 17KSPS
• Interface Type: Serial (3-Wire)
• Single Supply Voltage (typ): 3/5V
• Dual Supply Voltage (typ): Not RequiredV
• Architecture: R-2R
• Power Supply Requirement: Single
• Output Type: Voltage
• Integral Nonlinearity Error: ±2LSB
• Single Supply Voltage (min): 2.7V
• Single Supply Voltage (max): 5.5V
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 14
• Package Type: SOIC N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD7394/AD7395
CS CLK
H
L
L
L
L
L
H
H
X
X
X
X
X
NOTES
1. + positive logic transition; – negative logic transition; X Don’t Care
2. Do not clock in serial data while level sensitive inputs LDA or LDB are logic LOW.
+
X
L
H
H
L
X
X
X
X
X
X
X
+
+
RS
H
H
H
H
H
H
H
H
H
L
L
X
+
+
MSB
X
X
X
X
X
X
X
X
X
H
H
L
L
X
SHDN
H
H
H
H
H
H
H
H
H
H
H
H
H
L
LDA,B
LDA,B
V
CLK
CLK
OUT
SDI
SDI
CS
RS
ZS
FS
SHDN
I
DD
LDA/B
H
H
H
H
L
L
H
L
X
H
X
H
X
t
LD1
–
D11
t
CSS
D10
Table I. Control Logic Truth Table
Figure 2. Timing Diagram
Figure 3. Timing Diagram
Serial Shift Register Function
No Effect
No Effect
No Effect
Shift-Register-Data Advanced One Bit Latched
Shift-Register-Data Advanced One Bit Transparent
No Effect
No Effect
No Effect
No Effect
No Effect
No Effect
No Effect
No Effect
No Effect
D9
t
CL
t
DS
D8
t
DH
D7
t
CH
–4–
D6
D5
t
LDW
D4
t
S
ERROR BAND
D3
1 LSB
t
SDR
D2
t
CSH
D1
D0
t
t
DAC Register Function
Latched
Latched
Latched
Transparent
Latched
Updated with Current Shift Register
Contents
Transparent
Loaded with 800
Latched with 800
Loaded with All Zeros
Latched All Zeros
No Affect
CLRW
LD2
t
S
H
H
REV. 0