AD7477ARTZ-REEL7 Analog Devices Inc, AD7477ARTZ-REEL7 Datasheet - Page 6

• Manufacturer Part Number: AD7477ARTZ-REEL7
• Description: IC,A/D CONVERTER,SINGLE,10-BIT,CMOS,TSOP,6PIN
• Manufacturer: Analog Devices Inc

Specifications of AD7477ARTZ-REEL7

• Number Of Bits: 10
• Sampling Rate (per Second): 1M
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 17.5mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: SOT-23-6
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7477CBZ - BOARD EVALUATION FOR AD7477
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TIMING SPECIFICATIONS
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
NOTES
1
2
3
4
5
6
7
8
Specifications subject to change without notice.
Figure 1. Load Circuit for Digital Output Timing Specifications
AD7476A/AD7477A/AD7478A
SCLK
CONVERT
QUIET
1
2
3
4
5
6
7
8
POWER-UP
Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
Mark/space ratio for the SCLK input is 40/60 to 60/40.
Minimum f
Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 1.8 V when V
Measured with 50 pF load capacitor.
t
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
time of the part and is independent of the bus loading.
t
See Power-Up Time section.
8
7
4
4
5
6
values also apply to t
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
2
8
SCLK
TO OUTPUT
at which specifications are guaranteed.
Limit at T
AD7476A/AD7477A/AD7478A
10
20
20
16
14
12
50
10
10
22
40
0.4 t
0.4 t
10
9.5
7
36
See Note 7
1
8
PIN
minimum values.
50pF
SCLK
SCLK
t
t
t
C
SCLK
SCLK
SCLK
L
200 A
200 A
MIN
, T
MAX
I
I
OL
OH
1.6V
1
(V
DD
= 2.35 V to 5.25 V; T
Unit
kHz min
kHz min
MHz max
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns min
ns max
ns min
µs max
–6–
3
3
Description
A, B Grades
Y Grade
AD7476A
AD7477A
AD7478A
Minimum Quiet Time Required between Bus Relinquish
and Start of Next Conversion
Minimum CS Pulse Width
CS to SCLK Setup Time
Delay from CS until SDATA Three-State Disabled
Data Access Time after SCLK Falling Edge
SCLK Low Pulse Width
SCLK High Pulse Width
SCLK to Data Valid Hold Time
V
3.3 V < V
V
SCLK Falling Edge to SDATA High Impedance
SCLK Falling Edge to SDATA High Impedance
Power-Up Time from Full Power-Down
DD
DD
A
= T
≤ 3.3 V
> 3.6 V
MIN
DD
8
DD
) and timed from a voltage level of 1.6 V.
to T
, quoted in the timing characteristics is the true bus relinquish
≤ 3.6 V
MAX
, unless otherwise noted.)
DD
= 2.35 V and 0.8 V or 2.0 V for V
DD
> 2.35 V.
REV. C