AD9518-2ABCPZ-RL7 Analog Devices Inc, AD9518-2ABCPZ-RL7 Datasheet - Page 10
![no-image](/images/manufacturer_photos/0/0/57/analog_devices_inc_sml.jpg)
AD9518-2ABCPZ-RL7
Manufacturer Part Number
AD9518-2ABCPZ-RL7
Description
6-Output Clock Generator With 2.8GHz
Manufacturer
Analog Devices Inc
Type
Clock Generator, Fanout Distributionr
Datasheet
1.AD9518-2ABCPZ-RL7.pdf
(64 pages)
Specifications of AD9518-2ABCPZ-RL7
Pll
Yes
Input
CMOS, LVDS, LVPECL
Output
LVPECL
Number Of Circuits
1
Ratio - Input:output
1:6
Differential - Input:output
Yes/Yes
Frequency - Max
2.33GHz
Divider/multiplier
Yes/No
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-LFCSP
Frequency-max
2.33GHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
AD9518-2
SERIAL CONTROL PORT
Table 13.
Parameter
CS (INPUT)
SCLK (INPUT)
SDIO (WHEN INPUT)
SDIO, SDO (OUTPUTS)
TIMING
PD, SYNC, AND RESET PINS
Table 14.
Parameter
INPUT CHARACTERISTICS
RESET TIMING
SYNC TIMING
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
Output Logic 1 Voltage
Output Logic 0 Voltage
Clock Rate (SCLK, 1/t
Pulse Width High, t
Pulse Width Low, t
SDIO to SCLK Setup, t
SCLK to SDIO Hold, t
SCLK to Valid SDIO and SDO, t
CS to SCLK Setup and Hold, t
CS Minimum Pulse Width High, t
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
Capacitance
Pulse Width Low
Pulse Width Low
LOW
HIGH
DH
SCLK
DS
)
S
, t
DV
H
PWH
Min
2.0
2.0
2.0
2.7
16
16
2
1.1
2
3
Min
2.0
50
1.5
Typ
110
2
110
2
10
20
2
Rev. A | Page 10 of 64
Typ
110
2
Max
0.8
1
Max
0.8
3
0.8
1
0.8
0.4
25
8
Unit
V
V
μA
μA
pF
ns
High speed
clock cycles
Unit
V
V
μA
μA
pF
V
V
μA
μA
pF
V
V
nA
nA
pF
V
V
MHz
ns
ns
ns
ns
ns
ns
ns
Test Conditions/Comments
CS has an internal 30 kΩ pull-up resistor
SCLK has an internal 30 kΩ pull-down resistor
Test Conditions/Comments
These pins each have a 30 kΩ internal pull-up
resistor
High speed clock is CLK input signal