AD9518-2ABCPZ-RL7 Analog Devices Inc, AD9518-2ABCPZ-RL7 Datasheet - Page 9
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AD9518-2ABCPZ-RL7
Manufacturer Part Number
AD9518-2ABCPZ-RL7
Description
6-Output Clock Generator With 2.8GHz
Manufacturer
Analog Devices Inc
Type
Clock Generator, Fanout Distributionr
Datasheet
1.AD9518-2ABCPZ-RL7.pdf
(64 pages)
Specifications of AD9518-2ABCPZ-RL7
Pll
Yes
Input
CMOS, LVDS, LVPECL
Output
LVPECL
Number Of Circuits
1
Ratio - Input:output
1:6
Differential - Input:output
Yes/Yes
Frequency - Max
2.33GHz
Divider/multiplier
Yes/No
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-LFCSP
Frequency-max
2.33GHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER NOT USED)
Table 11.
Parameter
LVPECL OUTPUT ADDITIVE TIME JITTER
CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER USED)
Table 12.
Parameter
LVPECL OUTPUT ADDITIVE TIME JITTER
CLK = 622.08 MHz; LVPECL = 622.08 MHz;
CLK = 622.08 MHz; LVPECL = 155.52 MHz;
CLK = 1.6 GHz; LVPECL = 100 MHz; Divider = 16
CLK = 500 MHz; LVPECL = 100 MHz; Divider = 5
CLK = 2.4 GHz; VCO DIV = 2; LVPECL = 100 MHz;
Divider = 12; Duty-Cycle Correction = Off
Divider = 1
Divider = 4
Min
Min
Typ
40
80
215
245
Typ
210
Rev. A | Page 9 of 64
Max
Max
Unit
fs rms
fs rms
fs rms
fs rms
Unit
fs rms
Test Conditions/Comments
Distribution section only; does not include PLL and
VCO; uses rising edge of clock signal
BW = 12 kHz to 20 MHz
BW = 12 kHz to 20 MHz
Calculated from SNR of ADC method; DCC not used
for even divides
Calculated from SNR of ADC method; DCC on
Test Conditions/Comments
Distribution section only; does not include PLL and VCO;
uses rising edge of clock signal
Calculated from SNR of ADC method
AD9518-2