AD9552BCPZ-REEL7 Analog Devices Inc, AD9552BCPZ-REEL7 Datasheet - Page 23

• Manufacturer Part Number: AD9552BCPZ-REEL7
• Description: Precision Clock Translator
• Manufacturer: Analog Devices Inc
• Type: Clock Generatorr

Specifications of AD9552BCPZ-REEL7

• Design Resources: Clock Distribution Circuit with Pin-Programmable Output Frequency, Output Logic Levels, and Fanout (CN0152)
• Pll: Yes
• Input: Clock, Crystal
• Output: CMOS, LVDS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 2:2
• Differential - Input:output: No/Yes
• Frequency - Max: 900MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-LFCSP
• Frequency-max: 900MHz
• Number Of Elements: 1
• Pll Input Freq (min): 6.6MHz
• Pll Input Freq (max): 112.5MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: LFCSP EP
• Output Frequency Range: 0 to 900MHz
• Operating Temperature Classification: Industrial
• Pin Count: 32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REGISTER MAP
A bit that is labeled “aclr” is an active high, autoclearing bit. When set to a Logic 1 state, the control logic automatically returns it to a
Logic 0 state upon completion of the indicated task.
Table 17. Register Map
Addr.
(Hex)
0x00
0x04
0x05
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
Register
Name
Serial port
control
Readback
control
I/O update
PLL charge
pump and
PFD
control
PLL charge
pump and
PFD
control
PLL charge
pump and
PFD
control
PLL charge
pump and
PFD
control
VCO
control
VCO
control
VCO
control
PLL control
PLL control
PLL control
PLL control
PLL control
PLL control
PLL control
PLL control
PLL control
Input
receiver and
band gap
XTAL
tuning
control
(MSB) Bit 7
0
Unused
Unused
Enable SPI
control of
charge
pump
current
Unused
Antibacklash control[1:0]
Calibrate
VCO (aclr)
Enable SPI
control
of OUT1
dividers
Receiver
reset (aclr)
Disable SPI
control of
XTAL tuning
capacitance
FRAC[3:0] (SDM fractional part)
MOD[3:0] (SDM modulus)
Bit 6
LSB first
Unused
Unused
Enable SPI
control of
antiback-
lash
period
CP offset
current
polarity
Enable
ALC
Unused
Unused
P
1
divider[4:0]
(00000 = maximum, 11111 = minimum)
Bit 5
Soft reset
(aclr)
Unused
Unused
Unused
CP offset current[1:0]
VCO level control[5:0]
CP mode[1:0]
Band gap voltage adjust[4:0]
(3.5 μA granularity, ~900 μA full scale)
VCO band control[6:0]
ALC threshold[2:0]
Charge pump current control[7:0]
FRAC[19:12] (SDM fractional part)
FRAC[11:4] (SDM fractional part)
Rev. C | Page 23 of 32
Bit 4
1
Unused
Unused
Unused
MOD[19:12] (SDM modulus)
MOD[11:4] (SDM modulus)
N[7:0] (SDM integer part)
(0.25 pF per bit, inverted binary coding)
XTAL tuning capacitor control[5:0]
Bit 3
1
Unused
Unused
Enable CP
mode
control
Enable CP
offset
current
control
Unused
Enable SPI
control of
output
frequency
Unused
Unused
Bit 2
Soft reset
Unused
Unused
PFD
feedback
input edge
control
Reserved
Unused
Enable SPI
control of
VCO
calibration
Bypass
SDM
Unused
P
Bit 1
LSB first
Unused
Unused
PFD
reference
input edge
control
Reserved
Unused
Boost VCO
supply
Unused
Disable SDM
Unused
0
divider[2:0]
Unused
(LSB)
Bit 0
Readback
control
(aclr)
Force VCO
to
midpoint
frequency
PLL lock
detector
power-
down
Enable SPI
control of
VCO band
setting
Reset PLL
P
control of
band gap
voltage
0
I/O update
Reserved
Unused
Unused
Enable SPI
1
divider[5]
AD9552
Default
0x18
0x00
0x00
0x80
0x30
0x00
0x00
0x70
0x80
0x80
0x00
0x80
0x00
0x00
0x20
0x00
0x01
0x00
0x20
0x00
0x80