AD9600ABCPZ-125 Analog Devices Inc, AD9600ABCPZ-125 Datasheet - Page 15

• Manufacturer Part Number: AD9600ABCPZ-125
• Description: 10Bit 125Msps Dual 1.8V PB Free ADC
• Manufacturer: Analog Devices Inc

Specifications of AD9600ABCPZ-125

• Number Of Bits: 10
• Sampling Rate (per Second): 125M
• Data Interface: Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 800mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 9. Interleaved Parallel LVDS Mode Pin Function Descriptions
Pin No.
ADC Power Supplies
ADC Inputs
20, 64
1, 21
24, 57
36, 45, 46
0
37
38
44
43
39
40
42
41
49
50
Mnemonic
DRGND
DRVDD
DVDD
AVDD
AGND
VIN + A
VIN − A
VIN + B
VIN − B
VREF
SENSE
RBIAS
CML
CLK+
CLK−
NOTES
1. DNC = DO NOT CONNECT.
2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE
(LSB) D0–
ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST BE CONNECTED TO
GROUND FOR PROPER OPERATION.
DRVDD
DCO–
DCO+
DNC
DNC
DNC
DNC
DNC
DNC
D0+
D1+
D2+
D1–
D2–
D3–
Figure 7. Interleaved Parallel LVDS Mode Pin Configuration (Top View)
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
Type
Ground
Supply
Supply
Supply
Ground
Input
Input
Input
Input
I/O
Input
Input
Output
Input
Input
PIN 1
INDICATOR
Description
Digital Output Ground.
Digital Output Driver Supply (1.8 V to 3.3 V).
Digital Power Supply (1.8 V Nominal).
Analog Power Supply (1.8 V Nominal).
Analog Ground. Pin 0 is the exposed thermal pad on the bottom of the package.
Differential Analog Input Pin (+) for Channel A.
Differential Analog Input Pin (−) for Channel A.
Differential Analog Input Pin (+) for Channel B.
Differential Analog Input Pin (−) for Channel B.
Voltage Reference Input/Output.
Voltage Reference Mode Select (see Table 11 for details).
External Reference Bias Resistor.
Common-Mode Level Bias Output for Analog Inputs.
ADC Master Clock True. The ADC clock can be driven using a single-ended CMOS
(see Figure 60 and Figure 61 for the recommended connection).
ADC Master Clock Complement. The ADC clock can be driven using a single-ended
CMOS (see Figure 60 and Figure 61 for the recommended connection).
EXPOSED PADDLE, PIN 0
(BOTTOM OF PACKAGE)
PARALLEL LVDS
Rev. B | Page 15 of 72
(Not to Scale)
AD9600
TOP VIEW
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SCLK/DFS
SDIO/DCS
AVDD
AVDD
VIN + B
VIN – B
RBIAS
CML
SENSE
VREF
VIN – A
VIN + A
AVDD
SMI SDFS
SMI SCLK/PDWN
SMI SDO/OEB
AD9600