AD9600ABCPZ-125 Analog Devices Inc, AD9600ABCPZ-125 Datasheet - Page 35

• Manufacturer Part Number: AD9600ABCPZ-125
• Description: 10Bit 125Msps Dual 1.8V PB Free ADC
• Manufacturer: Analog Devices Inc

Specifications of AD9600ABCPZ-125

• Number Of Bits: 10
• Sampling Rate (per Second): 125M
• Data Interface: Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 800mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DC CORRECTION
Because the dc offset of the ADC may be significantly larger
than the signal being measured, a dc correction circuit is included
to null the dc offset before measuring the power. The dc correction
circuit can also be switched into the main signal path, but this
may not be appropriate if the ADC is digitizing a time-varying
signal with significant dc content, such as GSM.
DC Correction Bandwidth
The dc correction circuit is a high-pass filter with a programmable
bandwidth (ranging between 0.15 Hz and 1.2 kHz at 125 MSPS).
The bandwidth is controlled by writing the 4-bit dc correction
bandwidth register located at Register 0x10C, Bits [5:2].
The following equation can be used to compute the bandwidth
value for the dc correction circuit:
where:
k is the 4-bit value programmed in Register 0x10C, Bits [5:2]
(values between 0 and 13 are valid for k; programming 14 or
15 provides the same result as programming 13).
f
DC Correction Readback
The current dc correction value can be read back in Register 0x10D
and Register 0x10E for Channel A and Register 0x10F and
Register 0x110 for Channel B. The dc correction value is a 10-bit
value that can span the entire input range of the ADC.
DC Correction Freeze
Setting the dc correction freeze bit (Bit 6 of Register 0x10C) halts
the dc correction at its current state and continues to use the last
updated value as the dc correction value. Clearing this bit restarts
dc correction and adds the currently calculated value to the data.
SMI SCLK/PDWN
CLK
SMI SCLK/PDWN
SMI SDO/OEB
SMI SDO/OEB
is the AD9600 ADC sample rate in hertz.
DC
SMI SDFS
SMI SDFS
_
Corr
_
BW
=
MSB
2
−
MSB
k
20 CYCLES
−
RMS/MS CH A
14
×
20 CYCLES
RMS/MS CH A
2
f
Figure 70. Signal Monitor SPORT Output Timing (RMS, Peak, and Threshold Enabled)
CLK
×
π
Figure 71. Signal Monitor SPORT Output Timing (RMS and Threshold Enabled)
LSB
16 CYCLES
LSB
PK CH A
16 CYCLES
THR CH A
16 CYCLES
THR CH A
Rev. B | Page 35 of 72
MSB
MSB
20 CYCLES
20 CYCLES
RMS/MS CH B LSB
RMS/MS CH B
DC Correction Enable Bits
Setting Bit 0 (the dc correction for SM enable bit) of Register 0x10C
enables the dc correction for use in the signal monitor calculations.
Setting Bit 1 (the dc correction for signal path enable bit) of
Register 0x10C enables the calculated dc correction value to
be added to the output data signal path.
SIGNAL MONITOR SPORT OUTPUT
The SPORT is a serial interface with three output pins:
SMI SCLK (SPORT clock), SMI SDFS (SPORT frame sync), and
SMI SDO (SPORT data). The SPORT is the master and drives
all three SPORT output pins on the chip.
SMI SCLK
The data and frame sync are driven on the positive edge of the
SMI SCLK. The SMI SCLK has three possible baud rates: 1/2, 1/4,
or 1/8 the ADC clock rate, based on the SPORT controls. In
addition, by using the SPORT SMI SCLK sleep bit, the SMI SCLK
can be gated to remain low when the signal monitor block is not
sending any data. Using this bit to disable the SMI SCLK when it is
not needed can reduce coupling errors in the return signal path.
Doing so, however, has the disadvantage of spreading the
frequency content of the clock; if desired, the SMI SCLK can be
left enabled to ease frequency planning.
SMI SDFS
The SMI SDFS is the serial data frame sync. It defines the start
of a frame. One SPORT frame includes data from both
datapaths. The data from Datapath A is sent just after the frame
sync, followed by data from Datapath B.
SMI SDO
The SMI SDO is the serial data output of the block. The data is sent
MSB first on the first positive edge after the SMI SDFS. Each data
output block includes one or more rms magnitude value, peak level
value, and threshold crossing value from each datapath in the stated
order. If enabled, the data is sent, rms first, followed by the peak
value and the threshold crossing value, as shown in Figure 70.
GATED, BASED ON CONTROL
LSB
GATED, BASED ON CONTROL
16 CYCLES
16 CYCLES
PK CH B
THR CH B
16 CYCLES
THR CH B
RMS/MS CH A
AD9600
RMS/MS CH A